Industrial extensions to university high level synthesis tools

Fuhrman, Thomas E.

doi:10.1145/127601.127725

Cited by 15 publications

(4 citation statements)

References 5 publications

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“…List Scheduling Algorithm under Latency Constraint (List-L) is implemented to find the minimum latency under given resource constraints. The algorithm tries to achieve the minimum latency with the available resources (Fuhrman, 1991). As the algorithm is a heuristic algorithm, the computed schedule may not have the minimum latency; however, it can deal with multiple operation types and multiple-cycle operation delays.…”

Section: Resource-constrained Scheduling Problemmentioning

confidence: 99%

Ayse

Ozturk

Karaagac

Koc

2014

International Journal of Technology and Educational Marketing

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This paper presents an educational Electronic Design Automation tool called AYSE (Automated SYstem Synthesis Environment). AYSE is developed to help undergraduate and graduate students better understand and implement fundamental concepts in digital electronic design and synthesis courses. It receives an intermediate format that represents the system behavior and a set of constraints as input; and generates the representation of the actual circuit using the electronic components (functional units, memory and steering logic components) available in its technology library. A user can load the input from an external file or utilize the graphical user interface (GUI). Similarly, the output can be displayed using GUI or written to a file. The user is able to interact with the tool during the synthesis process and select the algorithms to perform three main synthesis tasks; namely, resource allocation, operation scheduling and resource binding/sharing. It is also possible to run the tool for the most efficient solution. The effectiveness of the tool was tested in a graduate level course.

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Section: Resource-constrained Scheduling Problemmentioning

confidence: 99%

Ayse

Ozturk

Karaagac

Koc

2014

International Journal of Technology and Educational Marketing

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“…This paper includes no discussion of specific tools used for this experiment because the discussion of the specific characteristic of these tools is not relevant for the contribution of this paper. For more information about behavioral synthesis flows the reader is referred to [1], [2], and for other comparisons between RTL and behavioral synthesis see [3], [4], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper

Moussa

Sugar

Suescun³

et al. 1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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This paper describes the experience and the lessons learned during the design of an ATM traffic shaper circuit using behavioral synthesis. The experiment is based on the comparison of the results of two parallel design flows starting from the same specification. The first used a classical design method based on RTL synthesis. The second design flow is based on behavioral synthesis. The experiment has shown that behavioral synthesis is able to produce efficient design in terms of gate count and timing while bringing a threefold reduction in design effort when compared to the RTL design methodology

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“…First, it applies to a system in actual use. The System Architect's Workbench high-level synthesis system has been used to produce layouts suitable for fabrication [15]; and it has been released to industry, where it has been used to design experimental chips [16,17]. Camposano's is the only other work that attempts to verify directly part of the operation of an automated register-transfer synthesis system in actual use.…”

Section: Introductionmentioning

confidence: 99%

Formal analysis of correctness of behavioral transformations

McFarland

1993

Form Method Syst Des

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Abstract. Much has been said about the importance of formal verification in hardware synthesis, but little has been done. Where it has been applied at all, it has only been used on simple, idealized examples. This paper describes the application of formal semantic analysis and verification to part of a working high-level synthesis system. The process revealed several significant errors in that system, errors that had previously been undetected. This experience leads to some reflections on the need for a rigorous, formal basis for hardware specification and synthesis, and on the value of formal techniques.

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Industrial extensions to university high level synthesis tools

Cited by 15 publications

References 5 publications

Ayse

Ayse

Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper

Formal analysis of correctness of behavioral transformations

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