Influence of encapsulation temperature on Ge:Pδ-doped layers

Abstract

We present a systematic study of the influence of the encapsulation temperature on dopant confinement and electrical properties of Ge:P ␦-doped layers. For increasing growth temperature we observe an enhancement of the electrical properties accompanied by an increased segregation of the phosphorous donors, resulting in a slight broadening of the ␦ layer. We demonstrate that a step-flow growth achieved at ϳ530°C provides the best compromise between high crystal quality and minimal dopant redistribution, with an electron mobility ϳ128 cm 2 / Vs at a carrier density 1.3ϫ 10 14 cm −2 , and a 4.2 K phase coherence length of ϳ180 nm.The recent demonstration of phosphorus in germanium ͑Ge:P͒ ␦-doped layers 1 and of atomic-scale scanning tunneling microscope ͑STM͒ hydrogen lithography on Ge͑001͒ ͑Ref. 2͒ has opened the possibility of an ultrahigh vacuum ͑UHV͒ STM approach to the fabrication of atomic-scale devices in Ge analogous to the one developed for atomic-scale devices in silicon. 3 This approach consists of using an STM to create a laterally patterned dopant ␦ layer which is then encapsulated under a homoepitaxial layer deposited by molecular beam epitaxy. The spatially defined ␦ layer is obtained by selective adsorption and incorporation of dopants on depassivated areas of a hydrogen-terminated Ge͑001͒ surface in which H atoms have been locally removed by an STM tip. Ge-based atomic scale devices are particularly interesting since the electronic device miniaturization to and beyond the 16-nm-node foresees the replacement of Si channel in transistors with higher mobility materials 4,5 and requires, ultimately, the development of technologies capable of miniaturizing devices at the atomic scale. 6 Any design of future atomic-scale Ge devices-such as ultrashallow abrupt junctions, ballistic transistors or quantum coherent devices-requires detailed knowledge of the carrier transport properties in the starting two-dimensional ͑2D͒ Ge:P ␦-doped layer as a function of the fabrication process parameters. Previous studies on Si:P ␦-doped layers have highlighted the crucial role of the temperature at which the encapsulation layer is grown ͑T g ͒ in determining the spatial confinement and electronic transport properties of dopants due to the interplay between epilayer crystal quality and dopant segregation. 7,8 Ideally one would need to carefully control the process thermal budget to find the maximum temperature that guarantees encapsulation of dopants in a highquality crystal while minimizing dopant redistribution. In silicon this has proven to be a difficult task: Si:P ␦ layers are typically encapsulated at low temperatures ͑ϳ250°C͒ to avoid P segregation at the expense of a rougher surface. 7-9 In this paper, instead, we demonstrate that for Ge:P ␦-doped layers a compromise between high crystal quality and minimal dopant redistribution is possible at a growth temperature ϳ530°C, sufficient to achieve a high-quality step-flow Ge growth. To this end we present a systematic study of the effect of Ge encapsulation temperatur...

Dual-temperature encapsulation of phosphorus in germanium δ‐layers toward ultra-shallow junctions

“…Raising the first growth temperature to 350 1C (sample D2) still gives a sharp peak with well defined edges. As expected, the peak maximum is smaller compared to that of sample D1 with N SIMS (D2) decreased to 1.3 Â 10 14 cm À 2 because of direct desorption of P from the surface prior to growth during the 530 1C pre-encapsulation anneal [14]. Onset of dopant segregation is indicated by the slight increase in the leading slope l L (D2) to $ 1.2 nm, obtained by fitting the profile over the depth range, where the P concentration increases steeply from 5 Â 10 18 to 2 Â 10 20 cm À 3 .…”

“…The substrate temperature is then raised, at a rate of 50 1C/min without growth interruption, up to a high temperature (HT) of 530 1C and then kept constant for the rest of the d-layer encapsulation until a total thickness of h¼25 nm is achieved. The LT/HT bounds of the growth temperature (T g ) profile were chosen based on our previous experiments on single-step growth [14], where deposition at 330 1C was proved to prevent dopant segregation while one at 530 1C was observed to be the lowest deposition temperature limit leading to atomically flat surfaces.…”

“…This technique utilizes in-situ adsorption of gaseous phosphine molecules onto a Ge (0 0 1) surface followed by thermal incorporation of the P atoms into the Ge matrix before encapsulation with an epitaxial Ge layer grown by low-temperature molecular beam epitaxy. With increase in encapsulation temperatures up to 600 1C, we observed an enhancement in the electrical properties of the d-layers due to the higher-quality crystal growth in the step-flow regime [14]. However encapsulation at higher temperatures was also accompanied by increasing dopant redistribution mainly due to the segregation of P atoms on the growing surface.…”

“…As a reference, we also include in Fig. 2 the previously published P depth profiles for sample S1, where no segregation was detectable at SIMS, and sample S2, showing instead increased dopant segregation [14].…”

(Invited) Advanced Germanium Epitaxy for Photonics Application

“…By the P4ALD process, P concentration of quarter of ML in a two dimensional plane is realized. By multiple P4ALD process with shallow spacer, it is possible to obtain heavy P concentration (10,17). Figure 9 shows SIMS depth profiles of P doped Ge without and with Si delta layers (12).…”