Influence of Etch Profiles on the Leakage Current and Capacitance of 3-D DRAM Storage Capacitors

Analysis of optical emission spectroscopy data during silicon etching in SF6/O2/Ar plasma

“…With the development of more advanced devices, the etching process faces more complex challenges [5,6]. One of the most well-known challenges is high aspect ratio (HAR) silicon etching, which is necessary to form sufficient capacitance and interconnections in the DRAM stacks [7,8]. In addition, it became necessary to isolate individual pixels in complementary metal oxide semiconductor (CMOS) image sensors and to achieve shallow trench isolation in CMOS to prevent electrical interference between devices [9,10].…”

Design optimization of heterojunction 1T DRAM cell with SiGe body/drain for high performance

“…To address these issues, high permittivity materials [5] and vertical structures with a high aspect ratio (e.g. trench and stacked structures [6,7]) have been adopted in state-of-the-art DRAM cell capacitors. However, owing * Author to whom any correspondence should be addressed.…”