Influence of Material Combinations on Delamination Failures in a Cavity-Down TBGA Package

Driel, W.D. van; Wisse, G.; Chang, A.Y.L.; Janssen, J.H.J.; Fan, Xuejun; Zhang, K.G.Q.; Ernst, L.J.

doi:10.1109/tcapt.2004.838859

Cited by 25 publications

(5 citation statements)

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“…In fact, no effective methodologies, models and tools are available for the prediction of the interfacial strength of these material combinations. We only use the normal stress strength of the interfacial bond as the failure criterion which may be quantified the strength of the interfaces [6] . In this article the finite element numerical simulation models have been established for the package bulging process.…”

Section: Model and Results Of Simulationmentioning

confidence: 99%

Failure Modes and FEM Analysis of Microelectronic Packaging

2006

KEM

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Based on the theory of thermo-elasticity mechanics, the finite element numerical simulation models have been established for the package bulging process. The mechanism of the interfacial void evolution is postulated. By taking the interface strength as function of process (moisture and temperature), it shows that the critical stress that results in the unstable void growth and delamination at the interface is significantly reduced and becomes comparable to the magnitude of the vapor pressure. The simulation result can make us understand the mechanism of the void-growth at the interface framework and provide data base for improving reliability of package and optimum design

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Section: Model and Results Of Simulationmentioning

confidence: 99%

Failure Modes and FEM Analysis of Microelectronic Packaging

2006

KEM

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Section: Informationmentioning

confidence: 99%

“…Interface shear stress or strain, von Mises stress, J-integrate and energy release rate were usual indicators to assess the delamination [5,[7][8][9][10][11]14]. While there were few papers about the effects of processes prior to molding on package delamination.…”

Section: Informationmentioning

confidence: 99%

“…If all interfaces in the package had perfect adhesions and the stresses were small, delamination was unlikely to occur. However, CTE mismatches between material couples, improper package structures, un-optimized process settings and extreme application environment with humidity or temperature cycling may result into strong interface stresses and package delamination [5][6][7][8][9][10][11][12][13].Some researchers used the method of finite element analysis (FEA) to predict the occurrence of delamination under different conditions. Interface shear stress or strain, von Mises stress, J-integrate and energy release rate were usual indicators to assess the delamination [5,[7][8][9][10][11]14].…”

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confidence: 99%

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Effects of alternating thermal stress on delamination between die attach and leadframe in SOIC package

Zong¹,

Wang²,

Xu³

et al. 2013

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

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Delamination was a critical failure to the microelectronics products, and it was introduced mainly by two factors: strong interface stress or poor interface adhesion. In this paper a tracking experiment confirmed the delamination between die attach and leadframe flag in a SOIC device, which occurred during wire bonding. Results of actual experiments and FEA found during the process flow, there were changes of structure profile as well as von Mises stress at the edge of die attach layer. This alternating stress was introduced by temperature cycling during D/A curing, wire bonding and following cooling; and resulted into the delamination at the interface, whose occurrence could be reduced when a higher peak temperature of D/A curing, a lower temperature of wire bonding, a thicker BLT or a CTE-lower die attach was applied. With a balance between delamination and other items, a final solution was proposed and got perfect results. InformationDue to the demands of higher integration level, higher power and lower cost in electronics industry, packaging technology and materials faced more and more challenges. Delamination was one common and critical failure, which may bring great destroys to the package [1-5]; such as die crack, wire bond lift or break, thermal and electrical performance degradation. If all interfaces in the package had perfect adhesions and the stresses were small, delamination was unlikely to occur. However, CTE mismatches between material couples, improper package structures, un-optimized process settings and extreme application environment with humidity or temperature cycling may result into strong interface stresses and package delamination [5][6][7][8][9][10][11][12][13].Some researchers used the method of finite element analysis (FEA) to predict the occurrence of delamination under different conditions. Interface shear stress or strain, von Mises stress, J-integrate and energy release rate were usual indicators to assess the delamination [5,[7][8][9][10][11]14]. While there were few papers about the effects of processes prior to molding on package delamination. This paper focused on the package delamination occurring before molding at the interface between die attach and leadframe flag. The results of actual experiments and FEA found the alternating interface stress, introduced by CTE mismatch and temperature cycling prior to molding, resulted into this delamination. At the same time, effects of some process factors were studied and a final solution was proposed to solve this delamination. BackgroundDuring the characterization of one small outline 28ld non exposed pad device, the package delamination between die attach and leadframe flag was found with through-scan CSAM

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“…Typical failure modes in BGA packages related to MSL performance are delamination between the moulding compound and the substrate (see Figure 2). Delamination at this interface is related to stitch failures after TMCL testing [2,3]. …”

Section: The Bga Package Familymentioning

confidence: 99%

Multi-Physics Based Structural Similarity Rules for the BGA Package Family

Driel

Mavinkurve²,

Gils³

et al.

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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To efficiently select qualification and reliability monitoring programs, structural similarity rules for Integrated Circuit designs, wafer fabrication processes and/or package designs are currently used by the industry. By following the package structural similarity rules, the numbers of reliability qualification tests may be greatly reduced. However, when looking at the present rules it is clear that they are not reliably defined. For instance, geometrical parameters such as die-topad ratio are not quantitatively included and it seems that linear relationships are assumed. Besides that, these rules are mainly deducted from experience and industrial trial and error results, not from reliability physics. Driven by the present development trends of microelectronics (miniaturization, integration, cost reduction, etc) it is urgently needed to develop 'multi-physics based structural similarity rules' based on reliability physics (physics of failures), to meet the industrial development trends. In this study, we have used DOE/RMS techniques to deduct advanced structural similarity rules through simulation-based optimisation techniques. Parametric 3D non-linear FE models are used to explore the responses of the complete BGA family for both the thermo-mechanical and moisture-diffusion responses as function of six parameters among which the die-to-pad ratio and the body size. In this way, advanced structural similarity rules are deduced which can be used to shorten design cycles. Even more, by using the accurate 3D nonlinear reliability prediction models an Excel-based tool is created for package designers. By using this tool, the number of reliability qualification tests can be reduced. More importantly, possible failure mechanisms can be (better) understood and predicted.

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Influence of Material Combinations on Delamination Failures in a Cavity-Down TBGA Package

Cited by 25 publications

References 6 publications

Failure Modes and FEM Analysis of Microelectronic Packaging

Failure Modes and FEM Analysis of Microelectronic Packaging

Effects of alternating thermal stress on delamination between die attach and leadframe in SOIC package

Multi-Physics Based Structural Similarity Rules for the BGA Package Family

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