Influence of oxidation temperature on the interfacial properties of n-type 4H-SiC MOS capacitors

Abstract

The effect of oxidation temperature on interfacial properties of n-type 4H-SiC metal-oxide-semiconductor capacitors has been systematically investigated. Thermal dry oxidation process with three different oxidation temperatures 1200 ℃, 1300 ℃ and 1350 ℃ were employed to grow SiO 2 dielectric, following by the standard post-oxidation annealing (POA) in NO ambience at 1175 ℃ for 2 hrs. The root mean square (RMS) roughness measured by Atomic Force Microscopy for the thermally grown SiO 2 before POA process is reduced with increasing the oxidation temperature, obtaining an atomically flat surface with a RMS of 0.157 nm from the sample oxidized at 1350 ℃. Several kinds of electrical measurements were used to evaluate the densities of near interface traps and effective fixed dielectric charge for the samples, exhibiting a trend reduced with increasing the oxidation temperature. The interface state density of 3×10 11 cm-2 eV-1 at 0.2eV from the conduction band edge was achieved from conductance method measurement for the sample oxidized at 1350 ℃. The results from Secondary Ion Mass Spectroscopy and X-ray Photoelectron Spectroscopy demonstrate that high oxidation temperature can reduce the width of transition layer, the excess Si and silicon suboxide compositions near the

Growth and characterization of nitrogen-phosphorus hybrid passivated gate oxide film on N-type 4H-SiC epilayer

“…The starting material used in this study was 4º off-axis 4H-SiC (0001) Si-face wafer with lightly doped n-type epilayer (thickness=5 μm, doping=1×10 16 , as previously reported [11,12]. It is inferred that the main effect of N passivation treatment is to reduce the NIETs within the transition layer which conforms to the results from Refs.…”

“…It is inferred that the main effect of N passivation treatment is to reduce the NIETs within the transition layer which conforms to the results from Refs. [11,13,14]. However, for the N&P hybrid passivation sample, the distribution of phosphorus is approximately uniform throughout the grown SiO 2 film with the concentration about 4×10 19 cm -3 to reach the interface (red line in Fig.…”

Effects of 5 MeV Proton Irradiation on Nitrided SiO2/4H-SiC MOS Capacitors and the Related Mechanisms

“…In the measurements, the gate voltage was swept from depletion to accumulation, and then swept back to depletion. The hysteresis voltage (∆V) is related to the un-trapped NIETs which could trap electrons at the accumulation condition [15]. The areal density of un-trapped NIETs can be calculated by (Cox/qS)•∆V, where Cox is oxide capacitance, q is electronic charge, S is area of oxide capacitance, as shown in Table 1.…”

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era in Power Industry

“…In 4H-SiC, typical oxidation temperature to grow a layer of native oxide is 1150°C. In some cases, it could be as high as 1300 or 1500°C which requires special oxidation furnaces, not the conventional quartz furnaces used for Si oxidation [38][39][40][41]. To use SiC devices to their full potential, we must continue to work to improve the electrical characteristics of the oxide/SiC interface by developing more effective processes to passivate defects at the interface formed during the oxidation process.…”