Influence of the surface morphology on the channel mobility of lateral implanted 4H-SiC(0001) metal-oxide-semiconductor field-effect transistors

Abstract

The influence of the surface morphology on the channel mobility of 4H-SiC metal-oxide-semiconductor field effect transistors annealed under two different conditions is discussed. The devices were fabricated using post-implantation annealing at 1650 °C. In particular, while the use of a protective capping layer during post-implantation annealing preserved a smooth 4H-SiC surface resulting in a channel mobility of 24 cm2 V−1 s−1, a rougher morphology of the channel region (with the presence of surface macrosteps) was observed in the devices annealed without protection, which in turn exhibited a higher mobility (40 cm2 V−1 s−1). An electrical analysis of SiO2/SiC capacitors demonstrated a reduction of the interface state density from 7.2 × 1011 to 3.6 × 1011 cm−2 eV−1, which is consistent with the observed increase of the mobility. However, high resolution transmission electron microscopy showed an almost atomically perfect SiO2/4H-SiC interface. The electrical results were discussed considering the peculiar surface morphology of the annealed 4H-SiC surfaces, i.e., attributing the overall reduction of the interface state density to the appearance of macrosteps exposing non-basal planes.

Atomic scale characterization of SiO2/4H-SiC interfaces in MOSFETs devices

“…As shown in Fig. 2b, in addition to the O distribution belonging to the SiO 2 , O is also detected on the side of 8 the APT reconstruction in the SiC region. It is due to the oxidation of the SiC between the end of the FIB preparation and the introduction in the APT system.…”

“…On the other hand, these compositional variations were not observed in later works. In fact, more recent works report that the low mobility is related to the roughness at the interface [8,9]. Note that the SiC/SiO 2 fabrication methods (substrate, post-implantation annealing, oxide growth method, post-annealing ambient) vary in all these studies.…”

Barrier Inhomogeneity of Ni Schottky Contacts to Bulk GaN

“…As a first step, a 800 nm silicon dioxide (SiO 2 ) hard mask has been deposited on the sample front‐side by a low‐temperature plasma enhanced chemical vapor deposition process, in order to keep protected the surface during the device processing. Then, a large area Ohmic contact was created on the wafer back‐side by the deposition of a Ti (15 nm )/Al (200 nm) /Ni (50 nm) /Au (50 nm) multilayer, followed by an annealing at 750 °C .…”

A look underneath the SiO2/4H-SiC interface after N2O thermal treatments

“…Cross-sectional scanning capacitance microscopy (SCM) was used to profile the active doping concentration in the SiC interfacial region of MOS devices, showing a higher compensation for the faceted sample than for the flat one. Recently, we demonstrated that MOS on the faceted surface exhibit also a lower interface-state density (≈3 × 10 11 cm −2 ·eV −1 ) with respect to devices on the flat surface (≈7 × 10 11 cm −2 ·eV −1 ) [12–13]. Here, both the different values of D it at SiO 2 /4H-SiC interface and the different doping in the near interface SiC region have been explained in terms of the peculiar surface morphology of faceted samples, assuming a preferential nitrogen incorporation in the 4H-SiC substrate when it exposes a larger percentile of (11−2 n ) planes.…”