InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration

Wang, Chuei-Tang; Tang, Tzu-Chun; Lin, Chun-Wen; Hsu, Ching‐Wei; Hsieh, Jeng-Shien; Tsai, Chung-Hung; Wu, Kai–Chiang; Pu, H. P.; Yu, Douglas

doi:10.1109/ectc.2018.00039

Cited by 47 publications

(7 citation statements)

References 14 publications

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“…Infineon introduced the fan-out WLB, which is referred to embedded wafer level ball grid array (eWLB) [26]. Another fan-out WLB technology, introduced by TSMC, is called integrated fan-out (INFO) package [27], [28]. On the one hand, WLB encapsulates the bare die chip and forms an IC protection.…”

Section: A State Of the Art Wafer Level Packagingmentioning

confidence: 99%

Broadband Low-Loss Fan-In Chip-to-Package Interconnect Enabling System-in-Package Applications Beyond 220 GHz

Pfahler,

Breun,

Engel

et al. 2024

Preprint

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This paper presents a broadband low-loss fanin wafer level ball grid array (WLB) vertical through-moldvia (TMV) interconnect that enables highly integrated systemin-package (SiP) applications beyond 220 GHz. The dedicate advantage of the proposed approach is to further minimize the separation between package components (e.g., antenna in package (AiP)) and on-chip receiver or transmitter chain. To demonstrate the robustness of the TMV interconnect design, the necessity for co-simulation of the integrated circuit (IC) package and the IC itself during the package-design is shown. Therefore, an in-depth analysis of the suppression of parasitic mode oscillation inside silicon is carried out. Furthermore, the parasitic radiation loss at the TMV interconnect discontinuity is given and a verification of the proposed TMV due to high agreement of simulation and measurement results is demonstrated. The interconnect has been verified with a measured 10 dB return loss bandwidth of 38 GHz and a de-embedded insertion loss of less than 2.8 dB at 275 GHz, which enables a compact low-loss broadband signal transition from active IC components in the backend-of-line (BEOL) to passive components in package. Compared to fan-out WLB, the developed fanin WLB solution enables higher integration density of active and passive components with the shortest interconnects for minimal insertion loss. Thus, the proposed fan-in TMV packaging provides a very compact, easy-to-assemble and cost-efficient alternative for SiP designs for future broadband communication and sensing solutions.

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Section: A State Of the Art Wafer Level Packagingmentioning

confidence: 99%

Broadband Low-Loss Fan-In Chip-to-Package Interconnect Enabling System-in-Package Applications Beyond 220 GHz

Pfahler,

Breun,

Engel

et al. 2024

Preprint

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show abstract

“…22 illustrates a conceptual diagram for one of the representative technologies (i.e., INFO process from TSMC) used to integrate multiple chiplets that are connected by a redistribution layer (RDL) with an ultrafine pitch [54]. The INFO package has been demonstrated to integrate antenna elements recently for millimeter-wave applications [55]. Another wafer level packaging technology, eWLB, has been under development and shown to support antenna integration at frequencies beyond 100 GHz for radar imaging applications [56].…”

Section: ) Wafer Level Packagementioning

confidence: 99%

Packaging and Antenna Integration for Silicon-Based Millimeter-Wave Phased Arrays: 5G and Beyond

2021

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“…Their objective is not to use TSVs for all the device chips. TSMC [149] demonstrated that the InFO_AiP (antenna-inpackage) for high performance and compact 5 G millimeter wave system integration is superior than that of solder bumped flip chip AiP on substrate as shown in Fig. 43.…”

Section: Opportunities For Fan-out Wafer-level Packagingmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration

Cited by 47 publications

References 14 publications

Broadband Low-Loss Fan-In Chip-to-Package Interconnect Enabling System-in-Package Applications Beyond 220 GHz

Broadband Low-Loss Fan-In Chip-to-Package Interconnect Enabling System-in-Package Applications Beyond 220 GHz

Packaging and Antenna Integration for Silicon-Based Millimeter-Wave Phased Arrays: 5G and Beyond

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

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