Information leakage from FPGA routing and logic elements

Giechaskiel, Ilias; Szefer, Jakub

doi:10.1145/3400302.3415695

Cited by 17 publications

(2 citation statements)

References 25 publications

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“…As it turns out, a long routing wire carrying a logical 1, reduces the delay of an adjacent long wire. This effect is studied in [27]. Having the exact information about wires and interconnects and wires, we could use assumptions on relative timing, which are available in Workcraft.…”

Section: Conclusion and Discussionmentioning

confidence: 99%

Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits

Kushnerov

Medina

Yakovlev

2021

2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazardfree MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.

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Section: Conclusion and Discussionmentioning

confidence: 99%

Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits

Kushnerov

Medina

Yakovlev

2021

2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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“…The possibility of remote measurement of the EM field emanated from an FPGA core is an open research question. However, the effects of the EM coupling between neighboring FPGA wires ( 5 ○ in Figure 6) can be measured remotely; it has been shown that the EM coupling between neighboring FPGA wires can leak information about the logical level carried by the observed wire [60,69]. Ramesh et al used an RO-sensor to learn the AES final round key.…”

Section: Dina G Mahmoud Vincent Lenders and Mirjana Stojilovićmentioning

confidence: 99%

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

Mahmoud

Lenders²,

Stojilović

2022

ACM Comput. Surv.

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Given the need for efficient high-performance computing, computer architectures combining central processing units (CPUs), graphics processing units (GPUs), and field-programmable gate arrays (FPGAs) are currently prevalent. However, each of these components suffers from electrical-level security risks. Moving to heterogeneous systems, with the potential of multitenancy, it is essential to understand and investigate how the security vulnerabilities of individual components may affect the system as a whole. In this work, we provide a survey on the electrical-level attacks on CPUs, FPGAs, and GPUs. Additionally, we discuss whether these attacks can extend to heterogeneous systems and highlight open research directions for ensuring the security of heterogeneous computing systems in the future.

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