InGaAs-InP core–shell nanowire/Si junction for vertical tunnel field-effect transistor

Abstract

Tunnel field-effect transistors (TFETs) have attracted much attention as building blocks for low-power integrated circuits because they can lower the subthreshold slope (SS) below the physical limitation of conventional FETs. There, however, remains a difficulty in increasing the tunnel current in TFETs since the energy gap at the tunnel junction has a unique probability. Here, we investigated the strain effect stemming from the InGaAs-InP core–shell (CS) structure on the tunneling current in a vertical TFET using an InGaAs nanowire (NW)/Si heterojunction. We found that the TFET demonstrated a 10-fold enhancement in current while achieving a steep SS (minimum SS = 41 mV/dec). Strain analysis for the InGaAs NW/Si tunnel junction revealed that specific strain induced at the junction affected the increase in the on-state current.

InP Low‐Dimensional Nanomaterials for Electronic and Optoelectronic Device Applications: A Review

“…[ 71 ] Low‐temperature electrical measurements suggests that the trap‐assisted tunneling effect associated with the narrow bandgap segment of InGaAsP dominated the electrical transport behaviors. In addition, heterojunctions related to InP NWs also reported for constructing electronic devices, such as InP/ZnS, [ 72 ] InAs/InP, [ 73 ] InP/InGaAs, [ 74 ] InGaAs‐InP, [ 75 ] etc.…”

III-V-on-Si transistor technologies: Performance boosters and integration

“…The reasons for the success of vertical nanowires here are that they can implement complex heterostructures with minimal defect formation as well as obtain highly scaled and electrostatically efficient gate-all-around channel structure. While several groups have now reported TFETs with subthermal operation, the question of the technological viability of TFETs remain [8], [64], [65]. To establish such viability, several challenges must be solved relating to CMOS compatibility, Si integration, self-aligned process steps, co-integration with MOSFETs and scalability.…”

Geometric effects on carrier collection in core–shell nanowire p–n junctions

“…Core-shell semiconductor nanowires (NWs) are an attractive alternative to planar devices for multiple applications, including field-effect transistors [1][2][3], photovoltaic devices [4,5], light-emitting diodes [6,7] and lasers [8,9]. Able to accommodate a large axial lattice-mismatch, combined with a large surface area, the core-shell lateral junction geometry enables electron-or photo-induced electron-hole pairs (EHPs) to be collected with shorter diffusion lengths due to the small NW diameter.…”