Inherent and stress-induced leakage in heavily doped silicon junctions

Hackbarth, E.; Tang, D.D.

doi:10.1109/16.8784

Cited by 58 publications

(16 citation statements)

References 14 publications

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“…The junction-tunneling current density Ji is critically dependent on the substrate acceptor concentration n, which must be increased to avoid punch-through as device dimensions are decreased [16][17][18][19][20][21][22]. The scaling law used in this study is plotted in Figure 9.6: (9.10) Given the doping density n, we can compute the depletion-layer thickness x for any potential ' l/J relative to substr ate using the usual step-j unction approximation: x= ~ y---g;;- .…”

Section: Io·' 10°mentioning

confidence: 99%

Scaling of MOS technology to submicrometer feature sizes

Mead

1994

Analog Integr Circ Sig Process

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Industries based on MOS technology now play a prominent role in t he developed and the developing world. j\fore importantly, MOS techn ology drives a large proportion of innovation in many technologies . It is likely th at the course of technological development depends more on the capability of MOS technology than on any other technical factor . T herefore, it is worthwhile investigating the na.ture and limits of future improvements to MOS fabrication. The key to improved MOS technology is r eduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at t he system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude wi th som e remarks on the system-level implications of fea.ture size as the minimum size approach es physical limits. IntroductionIt is always difficult . to nredict the future; few attemp ts to do so have met with resounding su ccess. One remarkable example of successful prediction is the exponential increase in complexity of integrated circuits, first noted by Gordon E . !vioor e. As we contemplate the ongoing evolution of this great technology, many questions arise: Can the trend continue? Will single-chip systems attain levels of complexity that render present system archit ectures unworkable [lj? vVill digital t.echniques completely replace analog methods [2]"7 The answers to these questions depend critically on the properties of the individual transistor s that provide the essential active functions, without which no interesting system beh avior is possible. Integrated-circuit density is increased by a reduction in the size of elementary feat.ures of the underlying structures; therefore, any discussion of the capabilities of future technologies must rely on an understanding of how the properties of transistors evolve as the transistor s' dimensions are made smaller.Elsewhere [3], we described the factors that limit how small an MOS transistor *Reproduced from Journal of VLSI Signal P rocessing, 8 , 9-25 (1994) Kluwer Academic Publishers, Boston. ~fanufacture d in The Netherlands.

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Section: Io·' 10°mentioning

confidence: 99%

Scaling of MOS technology to submicrometer feature sizes

Mead

1994

Analog Integr Circ Sig Process

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“…As can be explained by the Shockley-Read-Hall (SHR) generation-recombination (G-R) mechanism, for reverse-biased junctions, generation overrides recombination. In this bias condition and under the maximum generation-rate approximation, the analytic expression of I gr (which holds for both junctions) is given by [5][6][7][8][9][10][11][12]:…”

Section: Bdj In Obscuritymentioning

confidence: 99%

“…the surface and sidewall components have not been separately extracted; 2. surface generation at the interface SiO 2 /Si-depleted has been neglected [12].…”

Section: I-v Measurementmentioning

confidence: 99%

“…7). Here we propose several possible remedies for high-contrast materials and good conductors, if they are included in the computation domain: (i) If the object geometry is rectangular on the mask surface, we can use the mapped PSTD along the x and y directions to help reduce the magnitude of the Gibbs phenomenon in the mapped space [12,14]; (ii) if the object geometry is not rectangular but can be handled with multidomain PSTD, we suggest using multidomain PSTD in the x and y directions; (iii) use regular Fourier PSTD for the x and y directions and then apply a low-pass filter to the final steady-state results contaminated by the Gibbs phenomenon. This may help restore the global exponential convergence property of the PSTD algorithm.…”

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confidence: 99%

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Modelling of the CMOS buried double-junction photodetector

Hanna¹,

Alquié²,

Vasilescu³

2005

Microw. Opt. Technol. Lett.

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fixed as ⌬t ϭ 0.5⌬z/c. Then the 2 nd -order Liao's T2 ABC is applied in the lower boundary where the material is air and the 2 nd -order Liao's T3 ABC is applied in the upper boundary where the material is glass, with a refractive index of 1.5.The stability criterion for the hybrid algorithm is given by Eq. (7), but Liao's ABC requires ⌬t ϭ 0.5⌬z/c. In general, if we assume ⌬x ϭ ⌬y, then we can obtain the following stability criterion for using Liao's ABC: ⌬x ϭ ⌬y Ն ⌬z ͱ6 Ϸ 1.283⌬z.This is generally satisfied since, in the x and y directions, a lower sampling rate is usually used to take the advantage of the PSTD algorithm.Because we use Fourier PSTD with a uniform grid in the x and y directions, the hybrid algorithm in this paper requires that the material contrast in the x and y directions is not too large. Otherwise, the severe Gibbs phenomenon will contaminate the simulation results. In our numerical experiments, we found that when skin depth of the absorbing layer is very small, in which the case Gibbs phenomenon is sure to appear, there are fairly large differences in the field values obtained via the hybrid method and those obtained via FDTD with smaller grid size (see Fig. 7). Here we propose several possible remedies for high-contrast materials and good conductors, if they are included in the computation domain: (i) If the object geometry is rectangular on the mask surface, we can use the mapped PSTD along the x and y directions to help reduce the magnitude of the Gibbs phenomenon in the mapped space [12,14]; (ii) if the object geometry is not rectangular but can be handled with multidomain PSTD, we suggest using multidomain PSTD in the x and y directions; (iii) use regular Fourier PSTD for the x and y directions and then apply a low-pass filter to the final steady-state results contaminated by the Gibbs phenomenon. This may help restore the global exponential convergence property of the PSTD algorithm. We expect to see more progress in these areas in the near future. CONCLUSIONIn this paper, we have applied a hybrid PSTD-FDTD algorithm for electrically large thin-plate problems. We adopted FDTD along the vertical direction of the thin plate and PSTD along the horizontal directions. This arrangement can combine the advantages of both the FDTD and PSTD algorithms. As an example application, we studied the near-field scattering of a photo mask, and the hybrid algorithm was shown to offer large savings in memory usage and computation time, as compared with the FDTD method.

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“…Hot-carriers can increase the interface trap densities locally, resulting in larger surface recombination velocities and increased recombination current within the emitter-base depletion region in much the same way' as radiation stress [l9,20]. In addition, injected carriers can become trapped in the oxide, either after surmounting the interfacial potential barrier or by tunneling through the barrier to traps in the oxide bandgap, where they can bend the energy bands and alter device characteristics [21]. Like radiation, hot-carrier stress degrades sthe current gain in BJTs by increasing the base current while affecting the collector current negligibly.…”

Section: Introductionmentioning

confidence: 99%

Synergetic effects of radiation stress and hot-carrier stress on the current gain of npn bipolar junction transistors

Witczak

Kosier

Schrimpf

et al. 1994

IEEE Trans. Nucl. Sci.

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The combined effects of ionizing radiation and hotcarrier stress on the current gain of npn bipolar junction transistors were investigated. The analysis was carried out experimentally by examining the consequences of interchanging the order in which the two stress types were applied to identical transistors which were stressed to various levels of damage. The results indicate that the hot-carrier response of the transistor is improved by radiation damage, whereas hot-carrier damage has little effect on subsequent radiation stress. Characterization of the temporal progression of hot-carrier effects revealed that hot-carrier stress acts initially to reduce excess base current and improve current gain in irradiated transistors. PISCES simulations show that the magnitude of the peak electric-field within the emitter-base depletion region is reduced significantly by net positive oxide charges induced by radiation. The interaction of the two stress types is explained in a qualitative model based on the probability of hot-carrier injection determined by radiation damage and on the neutralization and compensation of radiation-induced positive oxide charges by injected electrons. The results imply that a bound on damage due to the combined stress types is achieved when hot-carrier stress precedes any irradiation.

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Inherent and stress-induced leakage in heavily doped silicon junctions

Cited by 58 publications

References 14 publications

Scaling of MOS technology to submicrometer feature sizes

Scaling of MOS technology to submicrometer feature sizes

Modelling of the CMOS buried double-junction photodetector

Synergetic effects of radiation stress and hot-carrier stress on the current gain of npn bipolar junction transistors

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