Initial Growth and Dislocation Accommodation of GaAs on Si(100) by Molecular Beam Epilaxy

Abstract

The nucleation and growth process of GaAs on Si has been studied by auger electron spectroscopy and transmission electron microscopy. At growth temperatures above 120°C, epitaxial growth begins with island formation, the size of which depends on the growth temperature. At low growth temperature(∼120°C) the epitaxial islands grow preferentially on Si surface terraces rather than on steps, and misfit dislocations are introduced at steps where the leading edges of growing islands come into contact with each other.

III–V-N compounds for multi-junction solar cells on Si

“…From the viewpoint of GaP nucleation, MBE growth under the high growth rate can give a high-nucleation density at the early stages of growth. However, since stacking faults (SFs) occur in the process, in which the three-dimensional island expands and coalesce[17,18], it is not desirable to growin MBE mode. While the conventional MEE can control generation of SFs and threading dislocations, but it leads to the pit formation by large surface migration length, meaning that the averaged lifetime of Ga adatom is long and the formation of Ga droplets becomes much easier at the early stages of growth.…”

Selective area metalorganic vapor-phase epitaxy of gallium arsenide on silicon

“…The deposition of a nucleation layer at reduced temperature followed by a thick layer deposited at elevated temperature is a well-known technique for growing III-V materials on Si [5,6,[8][9][10]23,30,31]. The temperature at which a film nucleates determines the density and size of 3D nuclei.…”

“…Takasugi and coworkers [31] have shown that nucleation at high temperature causes large GaAs nuclei to form that accommodate strain by forming ''type II'' dislocations, i.e. stacking faults, micro-twins, and threading dislocations inside the island.…”

High-Quality GaAsxP1-x/In0.13Ga0.87P Quantum Well Structure Grown on Si Substrate with a Very Few Threading Dislocations

“…As a result, a large number of threading dislocations are generated in the grown 3D islands and by the coalescence of 3D islands. 2,3,18) A tangle of dislocations is observed in the vicinity of the GaAs-Si interface, and no misfit dislocations are observed along the [011] direction. On the other hand, in the growth of the GaAs x P 1−x /In 0.13 Ga 0.87 P QW structure-on-Si, the lattice mismatch of 1.4% was accommodated by introduc- mismatch at heterointerfaces is 0.9%.…”

“…1) In the direct growth of GaAs-on-Si, however, a three-dimensional (3D) growth mode occurs at the initial growth stage and a large number of threading dislocations are generated in the GaAs layer. 2,3) These threading dislocations must be eliminated, since they degrade the performances of minority carrier devices such as laser diodes (LDs) and light-emitting diodes during their operation. Thus, many attempts have been made to reduce the threading dislocation density by thermal annealing and by inserting strained-layer superlattices (SLSs).…”