Instruction fetch and dispatch scheme with flag-in-cache/in-IBR

Abstract

We propose an instruction fetch‐and‐dispatch scheme containing (1) a flag‐in‐cache/in‐IBR scheme, where the sequential flag contained inside the instruction cache is jointly used with a parallel execution check and (2) a dynamic nullified prediction scheme, where a prediction of a nullified branch instruction is performed by using a branch history table. Using this scheme instructions can be fed effectively to multiple ALUs without lowering the operating frequency in super scalar processors where multiple instructions can be parallel processed in a single cycle. This scheme is applied to a 0.3‐μm CMOS, 4.5‐M transistors, 2‐instruction parallel processing, super scalar processor, and an operating frequency of 150 MHz is attained which confirms its effectiveness. © 1998 Scripta Technica, Syst Comp Jpn, 29(4): 86–94, 1998