Instruction reliability analysis for embedded processors

Azarpeyvand, Ali; Salehi, Mostafa E.; Firouzi, Farshad; Yazdanbakhsh, Amir; Fakhraie, S.M.

doi:10.1109/ddecs.2010.5491824

Cited by 14 publications

(4 citation statements)

References 17 publications

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“…The execution time of the tasks are obtained from the real value of six types of benchmark tasks (Fibonacci sequence, Bubble Sorting, Factorial Function, Multiplying Matrix Function, Newton Root and Sum of Squares) and AVF of these tasks are calculated by the method in [18] [19][20] [21]. The results are obtained by taking average of 10 times repetition.…”

Section: Methodsmentioning

confidence: 99%

“…However, it is assumed that every task of the application can be executed on any processor, even though the completion times on different processors may be different. As it is shown in [6][18] [19], the transient fault probability that may happen in transistors, gates and even a bit, is called Architectural vulnerability factor (AVF). By averaging over time, this factor can define the rate of soft errors that can appear on a core; while it runs a task.…”

Section: Introductionmentioning

confidence: 99%

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Fault tolerant task scheduling algorithm for multicore systems

Shiravi

Salehi

2014

2014 22nd Iranian Conference on Electrical Engineering (ICEE)

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Since the Reliability is a significant need for most of the Multicore systems, using fault-tolerant techniques such as hardware replication and software re-execution have been prevalent. This paper presents an adaptive fault-tolerant task scheduling algorithm that is a combination of TMR and DMR algorithms, in which Architectural Vulnerability Factor is considered in scheduling decisions, besides EDF and LLF scheduling algorithms. The proposed algorithm has been evaluated and compared with TMR and DMR methods in total execution time and processing cores utilization considering 3 to 8 cores. According to the results our proposed fault-tolerant methods outperforms both TMR and DMR methods about 35% in average.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fault tolerant task scheduling algorithm for multicore systems

Shiravi

Salehi

2014

2014 22nd Iranian Conference on Electrical Engineering (ICEE)

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“…Low Read SNM for Conventional 6T SRAM Cell In deep submicron, soft errors are an important reliability challenge for CMOS integrated circuits and some margin is needed to make the circuit more reliable against them [9]. Conventional 6T SRAM cell has good Hold SNM (HSNM) but it suffers from very low SNM for Read especially in low voltages.…”

Section: Bmentioning

confidence: 99%

A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS

Pasandi

Fakhraie

2013

2013 21st Iranian Conference on Electrical Engineering (ICEE)

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In this paper we present a new Static Random Access Memory (SRAM) that has 7 transistors in each cell. This idea allows for bit-interleaving that makes the SRAM more reliable against the soft errors. One of the challenges of a conventional 6 transistor (6T) SRAM cell in sub-threshold region is sizing of its access transistors. Here by separating access transistors of reading and writing, we mitigate this challenge. By using a minimum-size access transistor for reading, probability of unsuccessful read reduces. To have a more successful write operation, we make one of the inverters of the cell that is fighting with the write access transistor, weaker during write operation by floating its supply voltage and ground rails. After write operation, this inverter returns back to normal mode. Simulation results in 90 nm CMOS technology show that our design satisfies 4.5-sigma criterion for reading and writing at supply voltage of 300 mV. Compared to conventional 6T SRAM cell, our design improves read-time and write-time significantly. For example at supply voltage of 500 mV, these improvements are 137 and 83 percents, respectively. Comparing power and energy consumption for single write operation of the proposed 7T SRAM cell at supply voltage of 300mV with conventional 6T SRAM cell at 800mV (i.e. minimum achievable voltage for this SRAM cell) shows improvements of 133.4X and 266.78X, respectively.

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“…Since the area of the static random access memory (SRAM) array is large and sizes of the SRAM cell transistors are small, the SRAMs are likely to be disturbed by incoming radioactive particles. These particles can potentially change the stored data in the cells located in the strike area [5]. This degradation is more severe for the half-selected SRAM cells during the write operation.…”

Section: Introductionmentioning

confidence: 99%

Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs

Pasandi

Pedram

2018

IET Circuits, Devices & Systems

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In static random access memory (SRAM), some cells are not selected for writing, but due to the distribution of the word line signals in the SRAM array, their word line signal is activated. Therefore, they may be mistakenly written. Such cells are called half-selected cells. This study presents two schemes, one for single-ended and the other for differential sensing SRAMs, to eliminate the half-selection disturbance. In the first proposed scheme, the content of the desired row of the SRAM array is read before the write operation and is written back on the corresponding write bitlines. This operation results in eliminating the possibility for noise to be written onto the half-selected cells. In the second scheme, a simple read operation is performed before the write operation. The authors applied their half-selection resilient schemes to 8 and 6 T SRAMs. Simulation results show that in the presence of radioactive particles, by applying their write-back scheme to 8 T SRAM and their read-before-write scheme to the conventional 6 T SRAM, the failure rate is reduced from an average of 56 and 20%, respectively, to 0. The proposed schemes do not degrade write-ability of the SRAM cells, and are bit-addressable. Moreover, their proposed schemes consume smaller amounts of power compared with their rivals.

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Instruction reliability analysis for embedded processors

Cited by 14 publications

References 17 publications

Fault tolerant task scheduling algorithm for multicore systems

Fault tolerant task scheduling algorithm for multicore systems

A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS

Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs

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