Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs

Pasandi, Ghasem; Pedram, Massoud

doi:10.1049/iet-cds.2017.0227

Cited by 21 publications

(7 citation statements)

References 28 publications

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“…Conventional 6T SRAM cell faces numerous challenges when operating at lower supply voltages. During write operation at low voltage, weak access transistors in the cell cannot break the feedback loop to enforce the data which leads to poor write-ability [15]. However, in sub-threshold operation, if the process variation effects are significant, the above-mentioned challenges become worse.…”

Section: Conventional 6t Sram Cellmentioning

confidence: 99%

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Single bit‐line 11T SRAM cell for low power and improved stability

Lorenzo

Pailly

2020

IET Computers & Digital Techniques

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This study aims for a new 11T static random access memory (SRAM) cell that uses power gating transistors and transmission gate for low leakage and reliable write operation. The proposed cell has a separate read and write path which successfully improves read and write abilities. Furthermore, it solves the row half select disturbance and utilises a row-based virtual ground signal to eliminate unnecessary bit-line discharge in the un-selected row, thus decreasing energy consumption. The cell also achieves low power due to the stack effect. To show the effectiveness of the cell, its design metrics are compared with other published SRAM cells, namely, conventional 6T, 10T, 9T, and power-gated 9T (PG9T). In standby mode, from 6.71 to 7.37% leakage power reduction is observed for this cell at an operating voltage of 1.2 V and 29.21 to 58.68% & 32.74 to 71.11% improvement for write & read power over other cells. The proposed cell exhibits higher write and reads static noise margins with an improvement of 13.54 and 63.28%, respectively, compared to conventional 6T SRAM cell. The cell provides write delay improvement from 29.77 to 49.40% and read delay improvement from 7 to 12% compared to 9T, 10T, and PG9T, respectively.

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Section: Conventional 6t Sram Cellmentioning

confidence: 99%

“…Moreover, energetic alpha particles, neutrons, cosmic rays, and protons can create disturbance in the stored data of the memory [15]. As the technology scales down, the disturbance in stored data increases [16] during a write operation in half selected SRAM cells as their WLs are activated.…”

Section: Introductionmentioning

confidence: 99%

Single bit‐line 11T SRAM cell for low power and improved stability

Lorenzo

Pailly

2020

IET Computers & Digital Techniques

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“…Soft error is one of the crucial concerns in SRAM and is more challenging in scaled technologies 12 . By scaling of technology disturbance caused by alpha particles, neutrons and heavy ions have been found to substantially rise 13 . Error correction code (ECC) is a technique to recover from these soft errors.…”

Section: Introductionmentioning

confidence: 99%

Half‐selection disturbance free 8T low leakage SRAM cell

Lorenzo

Paily

2022

Circuit Theory & Apps

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Summary This work presents a robust and low leakage new 8T static random access memory (SRAM) cell without any half‐selection disturbance. The proposed cell removes write disturbance by eliminating the trail from supply and ground. Furthermore, it removes the read disturbance by separating the read trail from the storage node. The proposed cell addresses the challenge of half select by using different control signals. The cell achieves low leakage because of virtual ground (VGND), series connected tail transistor, and access series stack transistors. To study the usefulness of the proposed SRAM, it is compared with 6T, 10T, 9T, PG9T, 7T, and 8T SRAM cells. The proposed SRAM minimizes leakage power, write power, and read power by 12.4%, 21.62%, and 29.06%. Furthermore, the proposed cell improves read and write noise margin by 57.19% and 19.96%, respectively, as compared to a conventional 6T SRAM. Again, the write energy consumption lowers to about 43.86× while read energy consumption 28.95× as compared to 10T SRAM.

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“…Reduction in supply voltage is one of the most effective methods to reduce power consumption. However, conventional 6T SRAM cannot operate successfully at the small supply voltages [8][9][10][11]. For example, in a 90 nm technology, the minimum supply voltage that the conventional 6T SRAM can be fully functional is 0.725 V [12].…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, some other designs focus on increasing the read static noise margin (RSNM) to tackle the problem of low RSNM, which is one of the main operational challenges of the conventional 6T SRAM at low supply voltages. Having low RSNM imposes some limitations on the reduction of the supply voltage in the conventional 6T SRAM cell [8,[17][18][19].…”

Section: Introductionmentioning

confidence: 99%

Low‐power data encoding/decoding for energy‐efficient static random access memory design

Pasandi

Mehrabi

Ebrahimi

et al. 2019

IET Circuits, Devices & Systems

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This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that are going to be written into the SRAM array. Using SRAM cells which are more energy-efficient in writing a '0' than a '1' benefits from this, resulting in a reduction in the total power and energy consumptions of the whole memory. The input data encoding is performed using a simple circuit, which is built of multiplexers and inverters. After the read operation, data will be returned back to its initial form using a low-power data decoding circuit. Simulation results in an industrial and a predictive CMOS technology show that the proposed design for SRAM reduces the energy consumption of read and write operations considerably for some standard test images as input data to the memory. For instance, in writing pixels of Lenna test image into this SRAM and reading them back, 15 and 20% savings are observed for the energy consumption of write and read operations, respectively, compared with the normal write and read operations in standard SRAMs.

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Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs

Cited by 21 publications

References 28 publications

Single bit‐line 11T SRAM cell for low power and improved stability

Single bit‐line 11T SRAM cell for low power and improved stability

Half‐selection disturbance free 8T low leakage SRAM cell

Low‐power data encoding/decoding for energy‐efficient static random access memory design

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