Integrated circuits for channel coding in 3G cellular mobile wireless systems

Thomas, Christina; Bickerstaff, M.; Davis, Linda M.; Prokop, Tomáš; Widdup, B.; Zhou, Ge; Garrett, David; Nicol, Chris

doi:10.1109/mcom.2003.1222732

Cited by 14 publications

(6 citation statements)

References 6 publications

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“…2) in order to meet the quest for bandwidth among different standards. The throughput can further be enhanced by adopting radix-4 computation as used in [6,7,9,13,23,27] where two trellis steps are computed in a single cycle as shown in Fig. 3.…”

Section: Radix-4 Map Decoding Algorithm Revisitedmentioning

confidence: 99%

“…This becomes more challenging if radix-4 implementation is taken into account. Many implementations [6,7,17,23] have focused the radix-4 implementation of turbo-decoding; however, they cover only one standard or they take either the most general interleaver implementation or pure LUT based implementation. The standards targeted in this paper have different types of algorithms for implementing the interleaving within turbo coding/de-coding.…”

Section: Introductionmentioning

confidence: 99%

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Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

Asghar

Saeed

et al. 2010

J Sign Process Syst

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This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbodecoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm 2 area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm 2 /Mbps and energy efficiency of 0.55 nJ/b/iter.

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Section: Radix-4 Map Decoding Algorithm Revisitedmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

Asghar

Saeed

et al. 2010

J Sign Process Syst

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“…Bickerstaff et al have proposed a unified architecture designed for UMTS base stations [1,2]. The main emphasis is on the multi-channel aspect, and the flexibility in coding schemes has not been handled in this work.…”

Section: State Of the Artmentioning

confidence: 99%

Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets

Krishnaiah

Engin

Sawitzki

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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The current trend in the consumer devices and communication service provider market is the integration of different communication standards within a single device (e.g. GSM phone with Bluetooth, WLAN and infrared interface) requiring tight integration of mobile broadcast, networking and cellular technologies within one product. Channel decoder is traditionally one of the most computationally intensive building block within digital receivers. The aim of this paper is to investigate the feasibility of a programmable channel decoder that can be dynamically reconfigured for decoding turbo and convolutionally encoded streams from various wireless standards. The architecture options are presented and the area costs and flexibility compared between the options. The resulting decoder architecture supports hardware resource sharing and reconfiguration between different standards and decoders and is more efficient in terms of silicon area than independent implementation of every decoder on the same IC.

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“…In [2,3], a few approximations have been applied to the radix-4 logsum to reduce the computational complexity. These approximations result in a radix-4 recursion unit architecture shown in Fig.…”

Section: Prior Radix-4 Logsum Implementationmentioning

confidence: 99%

“…In [2,3], a radix-4 Turbo decoder architecture was presented. Based on this architecture, a radix-4 architecture is proposed in this paper, which significantly reduces the critical path delay, and hence achieves higher decoding throughput.…”

Section: Introductionmentioning

confidence: 99%

High-Throughput Radix-4 logMAP Turbo Decoder Architecture

Zhang

Parhi

2006

2006 Fortieth Asilomar Conference on Signals, Systems and Computers

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Turbo codes are one of the most powerful error correcting codes. This paper presents a high-throughput radix-4 logMAP Turbo decoder architecture based on the Lucent's radix-4 logMAP Turbo decoder architecture. It increases the throughput by 76% as compared to a radix-2 logMAP Turbo decoder. Compared with Lucent's radix-4 architecture, it increases the throughput by 32% with only a moderate increase in area.

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Integrated circuits for channel coding in 3G cellular mobile wireless systems

Cited by 14 publications

References 6 publications

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets

High-Throughput Radix-4 logMAP Turbo Decoder Architecture

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