Integrated frequency synthesiser in SiGe BiCMOS technology for 60 and 24 GHz wireless applications

Peters, Frank; Glisic, Srdjan; Winkler, Wolfgang

doi:10.1049/el:20073834

Cited by 12 publications

(10 citation statements)

References 3 publications

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“…This will minimize the charge pump mismatch for all PLL output frequencies. The PLL phase noise performance [8] compares favourably with most previously published silicon-based integrated mm-wave PLLs [13].…”

Section: Measurementsmentioning

confidence: 55%

“…The first version has no biasing resistors and has been described in [8]. Measured phase noise at 1 MHz offset was below -98 dBc/Hz over a tuning range from 47.2 to 49.6 GHz.…”

Section: Measurementsmentioning

confidence: 99%

“…This reduces power consumption, complexity, facilitates image rejection and eliminates LO pulling in transmitters. A first 48 GHz silicon-based PLL was presented in [8]. The performance requirements imply several conflicting demands such as a wide tuning range, low phase noise, low spur level, low power consumption, predictable settling behavior, and low complexity.…”

Section: Introductionmentioning

confidence: 99%

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A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth

Peters¹,

Glisic²,

Osmany³

et al. 2008

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 µm SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel charge pumps one of which dominates the loop dynamics and is biased at optimum output voltage. This equalizes the loop bandwidth and reduces charge pump mismatch.

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Section: Measurementsmentioning

confidence: 55%

“…The first version has no biasing resistors and has been described in [8]. Measured phase noise at 1 MHz offset was below -98 dBc/Hz over a tuning range from 47.2 to 49.6 GHz.…”

Section: Measurementsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth

Peters¹,

Glisic²,

Osmany³

et al. 2008

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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“…3,4 However, their research concentrates only on the PLL architectures and circuit blocks regardless of the channel selection in the synthesizer. In addition, there is no proper frequency planning for the synthesizer.…”

Section: Introductionmentioning

confidence: 99%

A SiGe 6 modulus prescaler for a 60 GHz frequency synthesizer

Kamal

Zhu

Al-Sarawi

et al. 2007

Microelectronics: Design, Technology, and Packaging III

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A prescaler is widely used in frequency synthesizers in order to handle channel selection. The division ratio has to be chosen carefully to achieve the desired frequency. In this paper, we present a 6 modulus prescaler in a 0.18 µm SiGe BiCMOS technology. The prescaler is part of a 60 GHz frequency synthesizer. In addition, we present a frequency planning for the 60 GHz frequency synthesizer. The prescaler employs an integer-N architecture. The circuit has a programmable divider with a division ratio of 7 and 8 and two counters to control the division ratio. The programmable divider utilizes ECL circuits, while the counters utilise CMOS circuits. Therefore an ECL-to-CMOS converter is used to bridge these two kinds of circuits. Simulation results show that the prescaler operates up to 4 GHz from a 1.8 V supply voltage.

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“…If a sliding Intermediate Frequency architecture as in [11] is used, a Phase Locked Loop of around 48 GHz including a 4x prescaler can be used to generate RF signals at f c = n x 5 x f crystal (n integer). All four centre frequencies of Fig.…”

mentioning

confidence: 99%

OFDM-Based Millimeter Wave System for High Data Rate WPAN Applications

Pagani

Piz²,

Siaud³

et al. 2008

2008 IEEE 68th Vehicular Technology Conference

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Millimeter wave wireless communications are opening the way towards high data rate applications for WPAN scenarios. Multi-Gbps wireless systems are currently defined by standardization bodies. This paper presents a complete 60 GHz OFDM PHY layer proposal fulfilling the requirements of the IEEE 802.15 Task Group 3c. Data rates are ranging from 335 Mbps to 3 Gbps, with a high level of scalability. The proposed system is designed to operate in the 57 to 66 GHz frequency band, with a possibility to use channel sizes of 1 GHz and 2 GHz. The OFDM PHY layer allows scalable spectrum efficiency to achieve high data rates with flexible radio coverage. For a nominal channel bandwidth of 1 GHz, the system uses an FFT size of 1024, convolutional coding and advanced interleaving schemes. Simulation results show that this system is well suited for very high data rate applications in realistic scenarios.

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Integrated frequency synthesiser in SiGe BiCMOS technology for 60 and 24 GHz wireless applications

Cited by 12 publications

References 3 publications

A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth

A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth

A SiGe 6 modulus prescaler for a 60 GHz frequency synthesizer

OFDM-Based Millimeter Wave System for High Data Rate WPAN Applications

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