Integrated instruction cache analysis and locking in multitasking real-time systems

Ding, Huijiang; Liang, Yun; Mitra, Tulika

doi:10.1145/2463209.2488916

Cited by 7 publications

(3 citation statements)

References 27 publications

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“…Thus, improving the behavior of the optimal single-content dynamic locking is not as straightforward as one could think. Indeed, studies claiming better results than single-content dynamic locking specifically state that they remove the line-buffer hardware component, required for locked caches to work properly [21].…”

Section: Placement Of Loading and Locking Pointsmentioning

confidence: 99%

“…Finally, some studies assume partial set-level lockable caches. For each cache set, these caches are able to track a variable number of non-locked lines sorted in LRU order, and lock the remaining ones [21,22]. Control complexity and storage to support this fine-grained locking-replacement surpasses the abilities of conventional caches and, of course, that of fully-lockable caches.…”

Section: Introductionmentioning

confidence: 99%

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Reducing the WCET and analysis time of systems with simple lockable instruction caches

et al. 2020

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One of the key challenges in real-time systems is the analysis of the memory hierarchy. Many Worst-Case Execution Time (WCET) analysis methods supporting an instruction cache are based on iterative or convergence algorithms, which are rather slow. Our goal in this paper is to reduce the WCET analysis time on systems with a simple lockable instruction cache, focusing on the Lock-MS method. First, we propose an algorithm to obtain a structure-based representation of the Control Flow Graph (CFG). It organizes the whole WCET problem as nested subproblems, which takes advantage of common branch-and-bound algorithms of Integer Linear Programming (ILP) solvers. Second, we add support for multiple locking points per task, each one with specific cache contents, instead of a given locked content for the whole task execution. Locking points are set heuristically before outer loops. Such simple heuristics adds no complexity, and reduces the WCET by taking profit of the temporal reuse found in loops. Since loops can be processed as isolated regions, the optimal contents to lock into cache for each region can be obtained, and the WCET analysis time is further reduced. With these two improvements, our WCET analysis is around 10 times faster than other approaches. Also, our results show that the WCET is reduced, and the hit ratio achieved for the lockable instruction cache is similar to that of a real execution with an LRU instruction cache. Finally, we analyze the WCET sensitivity to compiler optimization, showing for each benchmark the right choices and pointing out that O0 is always the worst option.

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Section: Placement Of Loading and Locking Pointsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reducing the WCET and analysis time of systems with simple lockable instruction caches

et al. 2020

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“…Our partial locking mechanism integrates cache locking with cache modeling, which allows us to estimate the WCET of predictable accesses through cache modeling and optimizes the WCET of unpredictable accesses through cache locking. Compared to full cache locking and static analysis, our partial locking technique achieves better results [7], [8].…”

Section: Introductionmentioning

confidence: 98%

WCET-Centric dynamic instruction cache locking

Ding¹,

Liang²,

Mitra³

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Cache locking is an effective technique to improve timing predictability in real-time systems. In static cache locking, the locked memory blocks remain unchanged throughout the program execution. Thus static locking may not be effective for large programs where multiple memory blocks are competing for few cache lines available for locking. In comparison, dynamic cache locking overcomes cache space limitation through timemultiplexing of locked memory blocks. Prior dynamic locking technique partitions the program into regions and takes independent locking decisions for each region. We propose a flexible loopbased dynamic cache locking approach. We not only select the memory blocks to be locked but also the locking points (e.g., loop level). We judiciously allow memory blocks from the same loop to be locked at different program points for WCET improvement. We design a constraint-based approach that incorporates a global view to decide on the number of locking slots at each loop entry point and then select the memory blocks to be locked for each loop. Experimental evaluation shows that our dynamic cache locking approach achieves substantial improvement of WCET compared to prior techniques.

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Time-sensitivity-aware shared cache architecture for multi-core embedded systems

Lee

Kim

2019

J Supercomput

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Integrated instruction cache analysis and locking in multitasking real-time systems

Cited by 7 publications

References 27 publications

Reducing the WCET and analysis time of systems with simple lockable instruction caches

Reducing the WCET and analysis time of systems with simple lockable instruction caches

WCET-Centric dynamic instruction cache locking

Time-sensitivity-aware shared cache architecture for multi-core embedded systems

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