WCET-Centric dynamic instruction cache locking

Ding, Huijiang; Liang, Yun; Mitra, Tulika

doi:10.7873/date.2014.040

Cited by 11 publications

(9 citation statements)

References 16 publications

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“…Ding et al [2012] point out that full cache locking may cause more cache misses that would have a negative effect on WCET reduction and propose a partial I-cache locking mechanism to lock parts of the I-cache. Ding et al [2014] propose a WCET-aware, dynamic I-cache locking approach for a single task. The approach uses ILP to determine the locking slots for each loop and selects the most profitable memory blocks to fill these slots.…”

Section: Related Workmentioning

confidence: 99%

WCET-Aware Dynamic I-Cache Locking for a Single Task

Zheng

Yang

2017

ACM Trans. Archit. Code Optim.

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Caches are widely used in embedded systems to bridge the increasing speed gap between processors and off-chip memory. However, caches make it significantly harder to compute the worst-case execution time (WCET) of a task. To alleviate this problem, cache locking has been proposed. We investigate the WCETaware I-cache locking problem and propose a novel dynamic I-cache locking heuristic approach for reducing the WCET of a task. For a nonnested loop, our approach aims at selecting a minimum set of memory blocks of the loop as locked cache contents by using the min-cut algorithm. For a loop nest, our approach not only aims at selecting a minimum set of memory blocks of the loop nest as locked cache contents but also finds a good loading point for each selected memory block. We propose two algorithms for finding a good loading point for each selected memory block, a polynomial-time heuristic algorithm and an integer linear programming (ILP)-based algorithm, further reducing the WCET of each loop nest. We have implemented our approach and compared it to two state-of-the-art I-cache locking approaches by using a set of benchmarks from the MRTC benchmark suite. The experimental results show that the polynomial-time heuristic algorithm for finding a good loading point for each selected memory block performs almost equally as well as the ILP-based algorithm. Compared to the partial locking approach proposed in Ding et al. [2012], our approach using the heuristic algorithm achieves the average improvements of 33%, 15%, 9%, 3%, 8%, and 11% for the 256B, 512B, 1KB, 4KB, 8KB, and 16KB caches, respectively. Compared to the dynamic locking approach proposed in Puaut [2006], it achieves the average improvements of 9%,

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Section: Related Workmentioning

confidence: 99%

WCET-Aware Dynamic I-Cache Locking for a Single Task

Zheng

Yang

2017

ACM Trans. Archit. Code Optim.

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“…It proposes a partial I-cache locking mechanism to lock a part of I-cache. [11] proposes a dynamic I-cache locking approach to minimize the WCET of a single task. It employs an ILP approach to determine the locking slots for each loop.…”

Section: Related Workmentioning

confidence: 99%

WCET-Aware Dynamic D-cache Locking for A Single Task

Zheng

2015

Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM

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Caches have been extensively used to bridge the increasing speed gap between processors and off-chip memory. However, caches make it much harder to compute the WCET (Worst-Case Execution Time) of a program. Cache locking is an effective technique for overcoming the unpredictability problem of caches. We investigate the WCET aware D-cache locking problem for a single task, and propose two dynamic cache locking approaches. The first approach formulates the problem as a global ILP (Integer Linear Programming) problem that simultaneously selects a near-optimal set of variables as the locked cache contents and allocates them to the D-cache. The second one iteratively constructs a subgraph of the CFG of the task where the lengths of all the paths are close to the longest path length, and uses an ILP formulation to select a nearoptimal set of variables in the subgraph as the locked cache contents and allocate them to the D-cache. For both approaches, we propose a novel, efficient D-cache allocation algorithm. We have implemented both approaches and compared them with the longest path-based, dynamic cache locking approach proposed in [22] and the static WCET analysis approach without cache locking proposed in [14] by using a set of benchmarks from the Mälardalen WCET benchmark suite, SNU real-time benchmarks and the benchmarks used in [27]. Compared to the static WCET analysis approach, the average WCET improvements of the first approach range between 11.3% and 31.6%, and the average WCET improvements of the second approach range between 12.3% and 32.9%. Compared to the longest path-based, dynamic cache locking approach, the average WCET improvements of the first approach range between 4.7% and 14.3%, and the average WCET improvements of the second approach range between 5.3% and 15.0%.

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“…Cache lockdown [4] divides the cache into way units and allocates available cache area to each core (or process). Cache lockdown is categorized as static locking or dynamic locking [32][33][34]. In the first case, dynamic locking [33] adaptively locks regions by profiling cache regions that are accessed while the system is executing.…”

Section: Related Workmentioning

confidence: 99%

“…Cache lockdown is categorized as static locking or dynamic locking [32][33][34]. In the first case, dynamic locking [33] adaptively locks regions by profiling cache regions that are accessed while the system is executing. In the other case, static locking [34] creates a cache memory map to be allocated to processes based on profiled log data before runtime.…”

Section: Related Workmentioning

confidence: 99%

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

et al. 2020

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Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

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WCET-Centric dynamic instruction cache locking

Cited by 11 publications

References 16 publications

WCET-Aware Dynamic I-Cache Locking for a Single Task

WCET-Aware Dynamic I-Cache Locking for a Single Task

WCET-Aware Dynamic D-cache Locking for A Single Task

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

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