Integrated optical interconnect for on-chip data transport

O’Connor, Ian; Tissafi-Drissi, F.; Navarro, David; Mieyeville, Fabien; Gaffiot, F.; Dambre, Joni; Wilde, M. De; Stroobandt, Dirk; Brière, M.

doi:10.1109/newcas.2006.250937

Cited by 16 publications

(8 citation statements)

References 13 publications

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“…The photodetector converts optical signals into electrical current which is then converted to electrical voltage by TIA. The subsequent LAs amplify the electrical voltage to the logic level [O'Connor et al 2006]. High-speed, low-power and small feature-size electronics and optical components are both required for optical links.…”

Section: Previous Workmentioning

confidence: 99%

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

et al. 2012

J. Emerg. Technol. Comput. Syst.

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Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance of floorplanning is overlooked. These significantly limit the power efficiency and performance of optical NoCs. In this work, we address these issues and propose a torus-based hierarchical hybrid optical-electronic NoC, called THOE. THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner. It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching fabric. Both of the unfolded and folded torus topologies are explored for THOE. Based on a set of real MPSoC applications, we compared THOE with a typical torus-based optical NoC as well as a torus-based electronic NoC in 45nm on a 256-core MPSoC, using a SystemC-based cycle-accurate NoC simulator. Compared with the matched electronic torus-based NoC, THOE achieves 2.46X performance and 1.51X network switching capacity utilization, with 84% less energy consumption. Compared with the optical torus-based NoC, THOE achieves 4.71X performance and 3.05X network switching capacity utilization, while reducing 99% of energy consumption. Besides real MPSoC applications, a uniform traffic pattern is also used to show the average packet delay and network throughput of THOE. Regarding hardware cost, THOE reduces 75% of laser sources and half of optical receivers compared with the optical torus-based NoC.

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Section: Previous Workmentioning

confidence: 99%

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

et al. 2012

J. Emerg. Technol. Comput. Syst.

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“…Optical NoCs are based on optical routers, optical waveguides and O/E interfaces. The technological and device aspects of a source-based optical link using heterogeneous integration for on-chip data transport was first presented in [6]. Some currently available technologies such as wavelength-division multiplexing (WDM) [7], [8] can be used in optical NoCs to increase the waveguide bandwidth.…”

Section: Introductionmentioning

confidence: 99%

Holistic comparison of optical routers for chip multiprocessors

et al. 2012

Anti-Counterfeiting, Security, and Identification

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Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of chip multiprocessors (CMPs). However, traditional NoCs using metallic interconnects consume a significant amount of power to deliver high communication bandwidth required in the near future. Optical NoCs are based on CMOS-compatible optical waveguides and optical routers, and promise significant bandwidth and power advantages. In this work, we review different designs of 5x5 and 4x4 optical routers for mesh or torus-based optical NoCs, and compare them for cost of optical resources and optical power loss. Besides, we use a 8x8 mesh-based optical NoC as a case study and analyze the thermal-induced power overhead while using different optical routers. Results show that the number of switching stages in an optical link directly affects the total optical power loss under thermal variations. By using passive-routing optical routers, the maximum number of switching stages in a XY-routing path is minimized to three, and the thermal-induced power overhead in the optical NoC is less than the matched networks using other routers.Index Terms-Chip multiprocessor, optical network-on-chip, optical router.

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“…We have studied passive type micro-resonator. Various structures of ONoC are proposed [2][3][4], which deal with the physical as well as system level design issues. The study showed a future scope in physical level analysis based on physical impairments such as crosstalk and other fiber losses.…”

Section: Introductionmentioning

confidence: 99%

Passive Micro-resonator based GMPLS Router for Optical Network-on-Chip

Patil

Chaudhari²

2011

NPA

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Generalized multiprotocol label switching (GMPLS) with wavelength division multiplexing (WDM) technology is a very promising protocol technology for future optical networks. GMPLS technology interconnects new and legacy networks by automating connection provisioning and traffic engineering. The present electrical interconnects for the system on chip (SoC) are unable to satisfy the multiple design requirements of bandwidth, data rate and latency. In this paper, for the first time we have proposed a micro resonator based GMPLS router for optical network on chip (ONoC). The evolution of such a router node on integrated circuit technology will cause the system design to move towards a communication-based architecture. The concept of an integrated GMPLS optical interconnect will be a potential technological solution, alleviating some of the more pressing issues involved in exchanging data between cores in SoC architectures. The investigation for ONoC was carried out at the physical level, where the system performance on the basis of crosstalk, blocking probability, offered traffic load and packet error rate (PER) was analyzed.

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Integrated optical interconnect for on-chip data transport

Cited by 16 publications

References 13 publications

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Holistic comparison of optical routers for chip multiprocessors

Passive Micro-resonator based GMPLS Router for Optical Network-on-Chip

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