Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits

Macii, Enrico; Bolzani, L.; Calimera, Andrea; Macii, Alberto; Poncino, Massimo

doi:10.1109/dsd.2008.90

Cited by 22 publications

(4 citation statements)

References 13 publications

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“…Although the technique is well-known, the research in this field is still ongoing [6]. An even more uncompromising method is power gating [7] where single parts of the design are cut off completely from the supply rails when not needed. This also saves the leakage current of the standard cells which gets more and more important in modern CMOS technologies.…”

Section: B Multistandard Digital Designmentioning

confidence: 99%

Wireless sensing by means of passive multistandard RFID tags

et al. 2009

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This paper presents a generic sensor interface built in a 0.13 µm CMOS process capable of being applied in passive HF & UHF RFID Tags without any additional power supply. The sensor interface contains an ultra low-power successive approximation ADC that uses the capacitive charge redistribution technique for its integrated DAC. An on-chip temperature sensor and up to three additional sensor signals can be applied to the ADC. A conversion rate of 100 kSps is reached while consuming less than 1.5 µA at 0.9 Volt supply voltage.

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Section: B Multistandard Digital Designmentioning

confidence: 99%

Wireless sensing by means of passive multistandard RFID tags

et al. 2009

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“…In [54], the integration of CG with PG is examined. In [54], the integration of CG with PG is examined.…”

Section: Clock Gating Integration With Leakage Reduction Techniquesmentioning

confidence: 99%

“…As fabrication technologies moved to deep sub-micron processes, static power consumption has become an important factor to total power and leakage reduction techniques emerged. In [54], the integration of CG with PG is examined. PG is a technique that completely shuts down the power supply of a circuit or a part of a circuit while it is in an idle mode, in order to mitigate static power overhead.…”

Section: Clock Gating Integration With Leakage Reduction Techniquesmentioning

confidence: 99%

Clock gating methodologies and tools: a survey

Pouiklis

2015

Circuit Theory & Apps

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Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Figure 3. Basic CG structure. A clock input and a CG function provide the Clk and En signals to the ICG (integrated CG), which generates the gated clock used by the registers. CLOCK GATING METHODOLOGIES AND TOOLS: A SURVEY 801consumption is getting higher on the priorities and risks, during specifications and requirements definition, meaning that power saving exploration needs to be exhaustive. Thus, the research space and tool development for CG applications and optimizations remain as relevant as ever. 816G. POUIKLIS AND G. CH. SIRAKOULIS

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“…These methods target the reduction of two different sources of power [9]. Moreover, the combination may help in reducing the area overhead associated to the insertion of the control logic of each individual technique.…”

Section: Combined Approachmentioning

confidence: 99%

Active-mode leakage power optimization using state-preserving techniques

Коршунов

Volobuev

2014

Proceedings of IEEE East-West Design &Amp; Test Symposium (EWDTS 2014)

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As technology sizes shrink, the developers come upon a problem of leakage currents. Among the different power reduction approaches there are power gating and clock gating, which can significantly eliminate (cut down) components of power consumption. The combined use of these approaches shows great promise. In fact, this good idea poses challenges due to some difficulties in practical integration. First, there is a need in additional control logic and timing overheads appear. Secondly, the flipflops need to be shut down during active-mode without any loss in logic states. We examine different statepreserving techniques that can retain data of flip-flops during the power gating. All presenting techniques can achieve leakage reduction in active mode of operation for combined approach.

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Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits

Cited by 22 publications

References 13 publications

Wireless sensing by means of passive multistandard RFID tags

Wireless sensing by means of passive multistandard RFID tags

Clock gating methodologies and tools: a survey

Active-mode leakage power optimization using state-preserving techniques

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