Integrating online and offline testing of a switching memory

Barbagallo, S.; Medina, D.; Corno, Fulvio; Prinetto, P.; Reorda, Matteo Sonza

doi:10.1109/54.655184

Cited by 10 publications

(8 citation statements)

References 6 publications

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“…In online checking, error detection is possible only during Read operations, therefore the time between the occurrence of an error and its detection, referred to as error detection latency, may be high. For applications with high reliability requirements, detection of erroneous data only at the moment when they are explicitly needed may not be acceptable [9]. In these cases, errors should be detected as early as possible to allow for recovery before the data are requested by the system.…”

Section: Introductionmentioning

confidence: 98%

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs

Voyiatzis¹,

Efstathiou²,

Sgouropoulou³

2014

2014 9th IEEE International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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An approach for periodic online testing of embedded DRAMs is presented. The fault-free memory contents are compressed, using accumulator-based response compaction, and periodically compared to subsequently compressed test data. The compressed signature is updated concurrently with write operations, without need for recomputing. Comparisons with previously proposed schemes indicate that the proposed scheme results in considerable savings in hardware overhead.

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Section: Introductionmentioning

confidence: 98%

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs

Voyiatzis¹,

Efstathiou²,

Sgouropoulou³

2014

2014 9th IEEE International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…But, since error detection is only possible during read operations, the time between the occurrence of an error and its detection, referred to as error detection latency, may be very high. For some applications with high reliability requirements, e.g., in telecommunication switching, it is not acceptable to detect erroneous data only at the moment when the data are explicitly needed [23]. In contrast, errors should be detected as early as possible to allow for recovery before the data are requested by the system.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of online BIST for different word sizes of memories

2014

IJRA

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Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST. Achieving considerable reduction in test time. Previous works or symmetric transparent BIST schemes require that a separate BIST module is utilized for each RAM under test. This approach, giver the large number of memories available in current chips, increase the hardware overhead of the BIST circuitry.In this work we propose a Symmetric transparent BIST scheme that can be utilized to test Rams. For 5 different word widths hence, more than one RAMs can be tested in a roving manner. The hardware overhead of the proposed scheme is considerably smaller compared to the utilization of previously proposed symmetric transparent schemes.

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“…But, since error detection is only possible during READ operations, the time between the occurrence of an error and its detection, referred to as error detection latency, may be very high. For some applications with high reliability requirements, e.g., in telecommunication switching, it is not acceptable to detect erroneous data only at the moment when the data are explicitly needed [3]. In contrast, errors should be detected as early as possible to allow for recovery before the data are requested by the system.…”

Section: Introductionmentioning

confidence: 99%

Efficient online and offline testing of embedded DRAMs

Hellebrand

Wunderlich

Ivaniuk

et al. 2002

IEEE Trans. Comput.

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AbstractÐThis paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

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Integrating online and offline testing of a switching memory

Cited by 10 publications

References 6 publications

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs

Design and implementation of online BIST for different word sizes of memories

Efficient online and offline testing of embedded DRAMs

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