2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) 2018
DOI: 10.1109/bcicts.2018.8550922
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Integration of SiGe HBT with <tex>$\text{f}_{\text{T}}=305\ \text{GHz},\ \text{f}_{\max}=537 \text{GHz}$</tex> in 130nm and 90nm CMOS

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Cited by 12 publications
(7 citation statements)
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“…All the circuits detailed in this article were developed and manufactured in the preproduction 90 nm SiGe:C BiCMOS technology B12HFC from Infineon Technologies AG [1], [2], [3]. In addition to some of the fastest bipolar transistors in SiGe with a transit frequency f T of 300 GHz and a maximum oscillation frequency f max ≥ 500 GHz, this technology provides p-n junction varactors, RF-MIM capacitors, and RF-TAN resistors.…”
Section: Circuit Designmentioning
confidence: 99%
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“…All the circuits detailed in this article were developed and manufactured in the preproduction 90 nm SiGe:C BiCMOS technology B12HFC from Infineon Technologies AG [1], [2], [3]. In addition to some of the fastest bipolar transistors in SiGe with a transit frequency f T of 300 GHz and a maximum oscillation frequency f max ≥ 500 GHz, this technology provides p-n junction varactors, RF-MIM capacitors, and RF-TAN resistors.…”
Section: Circuit Designmentioning
confidence: 99%
“…C IRCUIT and system designers have increasingly focused on the terahertz (THz) frequency range in the past few years. Recent developments in semiconductor technologies [1], [2], [3] enable circuits and systems beyond the millimeterwave (mmWave) band (30 − 300 GHz) and deep into the THz frequency band between 0.3 and 3 THz [4], [5], [6], [7], [8]. The THz band has multiple advantages for applications like sensing and communication, such as the large available bandwidth or the small wavelength enabling massive MIMO arrays for small-scale systems.…”
Section: Introductionmentioning
confidence: 99%
“…The 90nm EBL BiCMOS process is based on Infineons 90nm automotive CMOS technology L90FLA and previously reported EBL HBT integration in a 130nm node (11). The HBT module is positioned after CMOS gate structuring but prior to lightly doped drain (LDD) and source drain implants (HDD), minimizing the impact on CMOS device parameters.…”
Section: Process Flow 90nm Bicmosmentioning
confidence: 99%
“…Following indications from previous studies the LDD anneal was reduced from 1025°C/5s to 1010°C/spike with the HDD anneal remaining unchanged at 1050°C/spike (11). After removing the excess dielectric layers from HBT and CMOS, the wafers continued into a standard 90nm CMOS mid of line process route with CoSix as silicide.…”
Section: Process Flow 90nm Bicmosmentioning
confidence: 99%
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