Intel 22nm FinFET (22FFL) Process Technology for RF and mm Wave Applications and Circuit Design Optimization for FinFET Technology

Lee, H.-J.; Rami, Said; Ravikumar, Surej; Neeli, Vijaya B.; Phoa, K.; Sell, B.; Zhang, Y.

doi:10.1109/iedm.2018.8614490

Cited by 73 publications

(24 citation statements)

References 5 publications

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“…Since DC parameters were well calibrated, G m R o of FinFETs and NSFETs were reasonable within the measured data [10], [11], [23]- [25]. F t and F max were slightly larger than the measured data [10], [11], [23]- [25] because the parasitic RC components of metal interconnects are not included in this TCAD work. But FinFETs and NSFETs would have the same metal-line configurations under the same CPP.…”

Section: Device Structure and Simulation Methodssupporting

confidence: 52%

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

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Analog/RF performances of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) were investigated and compared thoroughly using fully-calibrated TCAD. NSFETs have greater current drivability and gate-to-channel controllability than FinFETs under the same footprint, thus achieving larger intrinsic gain. But the cutoff frequencies (F t) of FinFETs and NSFETs are comparable due to larger gate capacitances (C gg) of NSFETs compensating DC performance improvements. Gate resistances (R g) of NSFETs are larger because of their metal gate (MG) configuration surrounding the channels, longer MG height by the topmost NS spacing region, and the bottom transistor, thus degrading maximum oscillation frequency (F max). Device design guidelines of FinFETs and NSFETs are also studied for better intrinsic gain, F t , and F max. Intrinsic gain is improved by better electrostatics, whereas F t increases by greater current drivability over C gg. For larger F max , careful device design is required to compensate between R g , C gg , output resistance, and F t. Overall, NSFETs outperform FinFETs in terms of intrinsic gain, F t , and F max , thus NSFETs are promising for analog/RF applications.

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Section: Device Structure and Simulation Methodssupporting

confidence: 52%

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

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“…This additional hardware overhead is also expected to significantly shrink with more advanced CMOS technology nodes. Note that the f max of the 65-nm CMOS process used in this work is only 280 GHz; with the recent development of FinFET (f max =450 GHz in [29]) and FDSOI (f max =370 GHz in [30]) CMOS technologies, the EIRP and NF are expected to improve significantly, too, which further make low-THz radar sensing more practical for emerging applications that require higher resolution and smaller form factor.…”

Section: Discussionmentioning

confidence: 99%

A 220-to-320-GHz FMCW Radar in 65-nm CMOS Using a Frequency-Comb Architecture

Wang

Chen

et al. 2021

IEEE J. Solid-State Circuits

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This paper presents a CMOS-based, ultrabroadband FMCW (frequency-modulated continuous-wave) radar using a terahertz (THz) frequency-comb architecture. The high-parallelism spectral sensing provided by this architecture significantly reduces the bandwidth requirement for the THz front-end circuitry and ensures that the peak output power and sensitivity are maintained across the entire band of operation. The speed and linearity of frequency chirping are also improved by the comb system. An antenna-sharing scheme based on a square-mixer-first architecture is used, which not only leads to compact size, but also facilitates the stitching of the multi-channel radar IF data. To avoid the usage of high-cost silicon lens in the on-chip broadband radiation, a multi-resonance substrate-integrated-waveguide (SIW) antenna structure is innovated, which provides 15% fractional bandwidth for impedance matching. As a proof-of-concept, a five-tone radar prototype that seamlessly scan the entire 220-to-320-GHz band is demonstrated. In the measurement, the multi-channel-aggregated EIRP (equivalent isotropically-radiated power) is 0.6 dBm, and is further boosted to ∼20 dBm with a TPX (polymethylpentene) lens. The measured minimum single-sideband noise figure (SSB NF) of the receiver, including the antenna loss and baseband amplifier, is 22.8 dB. Due to the comb-architecture, the EIRP and NF values fluctuate by only 8.8 and 14.6 dB, respectively, across the 100-GHz bandwidth. The chip has a die size of 5 mm 2 and consumes 840 mW of DC power. This work marks the first CMOS demonstration of THz radar, and achieves record bandwidth and ranging resolution among all radar front-end chips.

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“…Silicon fin field-effect transistors (FinFETs) have been scaled down to 10-nm node [1], and further down to 5-nm node by full-fledged EUV and SiGe channel [2]. Moreover, RF devices have adopted fin structure to improve the gate electrostatics and to increase the current drivability for analog/RF applications [3]- [5]. But it is challenging to scale down the devices while maintaining analog/RF performances in order to contain all chipsets including longterm evolution and 5G bands within a small mobile device.…”

Section: Introductionmentioning

confidence: 99%

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Yoon

Baek

2020

IEEE Access

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A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (G m) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (R o) by dual-WF scheme and thus achieve larger intrinsic gain (A V = G m R o). Smaller G m and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large R o increases the maximum frequency (F max). Especially, 2-CAS has larger A V and F max than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.

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Intel 22nm FinFET (22FFL) Process Technology for RF and mm Wave Applications and Circuit Design Optimization for FinFET Technology

Cited by 73 publications

References 5 publications

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

A 220-to-320-GHz FMCW Radar in 65-nm CMOS Using a Frequency-Comb Architecture

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

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