Interconnect driver design for long wires in field-programmable gate arrays

Lee, Myeong Soo; Lemieux,; Mirabbasi,

doi:10.1109/fpt.2006.270299

Cited by 18 publications

(11 citation statements)

References 33 publications

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“…We note that [5] considered the FPGA interconnect design problem to insert and size buffers to optimize the delay from the start of the interconnect wire to its end. The methods in [5] are ad hoc in nature.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…The methods in [5] are ad hoc in nature. In one method, it assumes that buffers can be inserted anywhere and it simply sweeps over all possible buffer sizes and locations to find the best solution.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…Each wire can transmit a signal starting at the driver point and exit at different output points. A transmitted signal which exits before the end point is said to make an early turn (ET) [5]. In this work, we only consider the unidirectional interconnect.…”

Section: Problem Definitionmentioning

confidence: 99%

“…A FPGA uses wires of different lengths connected by programmable switches. In this paper, we consider the unidirectional wires, such as the ones in [4,5,6] where the signal can propagate from the source to some intermediate points or to the end of the wire. Recently, the design and optimization of FPGA buffered long interconnect was addressed in [5].…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we consider the unidirectional wires, such as the ones in [4,5,6] where the signal can propagate from the source to some intermediate points or to the end of the wire. Recently, the design and optimization of FPGA buffered long interconnect was addressed in [5]. While they acknowledged that the right target should be the minimization of the arrival times of a signal at different points of a long wire, their proposed methods still only optimized the signal propagation delay from the start of the interconnect wire to its end.…”

Section: Introductionmentioning

confidence: 99%

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Optimal Buffering of FPGA Interconnect for Expected Delay Optimization

He¹,

Mak

2007

2007 International Conference on Field-Programmable Technology

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The designers of field-programmable gate arrays (FPGAs) always devote to optimize the chip performance. The interconnect delay is a crucial determining factor of circuit performance in FPGA based design. In FPGAs, signals passing through a long wire do not always exit at the end of the wire. Therefore, the expected delay other than end to end delay of the long wire should be optimized. This paper is the first work that addresses expected delay optimization for FPGA interconnect. We present an optimal dynamic programming based approach to insert and size buffers to minimize the expected delay. The experimental results showed that the expected delay of the interconnect buffered with consideration of expected delay optimization sometimes can be significantly smaller than the interconnect buffered for end-to-end delay minimization. KEY WORDS FPGA, long interconnect, buffer insertion, expected delay optimization

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Section: Proposed Methodsmentioning

confidence: 99%

Section: Proposed Methodsmentioning

confidence: 99%

Section: Problem Definitionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Optimal Buffering of FPGA Interconnect for Expected Delay Optimization

He¹,

Mak

2007

2007 International Conference on Field-Programmable Technology

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Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Lee

Lemieux

Mirabbasi

2007

J Sign Process Syst Sign Image

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Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end multiplexing and driving logic, Bfinite^wire length, and a discrete number of repeaters. A metric introduced during the design is the Bpath delay profile^, or the arrival time of a signal at different points of a long wire. This method is used to design buffering strategies for interconnect based on 0.5, 2, and 3 mm wire lengths in 180 nm technology. These interconnect designs are coded into VPR along with an improved timing analyzer which accurately determines the Bpath delay profile^arrival times. Using VPR, average critical-path delay is reduced by 19% for 0.5 mm wires and by up to 46% for 3mm wires over previous designs.

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