Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs

Abstract

Interposer-based 2.5-D integrated circuits (ICs) are seen today as a first step toward the eventual industry adoption of 3-D ICs based on through-silicon vias (TSVs). The TSVs and the redistribution layer (RDL) in the silicon interposer, and micro-bumps in the assembled chip must be adequately tested for product qualification. We present an efficient interconnecttest solution that targets TSVs, RDL wires, and micro-bumps for shorts, opens, and delay faults. The proposed test technique is fully compatible with the IEEE 1149.1 Standard. To reduce test cost, we also present a test-path design and scheduling technique that minimizes a composite cost function based on test time and the design-for-test overhead in terms of additional TSVs and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a single test path. We present simulation results to demonstrate the effectiveness of fault detection, and synthesis results to evaluate the hardware cost per die relative to the IEEE 1149.1 Standard. We also present test-path design and test-scheduling results to highlight the effectiveness of the optimization technique.Index Terms-2.5-D IC, boundary scan, interconnect test, silicon interposer, test-path scheduling.

Testing of Interposer-Based 2.5D Integrated Circuits

“…Chapter 2-7 present results obtained in the course of the thesis research. These results have been published in [33][34][35][36][37][38][39][40][41][42]. Chapter 8 summarizes the contributions of the dissertation and describes directions for future research.…”

“…InTest can be carried out more easily because the internal logic of each tile is independent from the other tiles. The InTest problem has been studied in various forms in previous work[2, 5,38]. Thus, each tile can be tested independently.…”

Physical Design Automation for 3D Chip Stacks

“…Fault models and at-speed testing has been proposed for both interposer stacks [84][85][86] and TSV-based 3D ICs [43,87,88]. These studies are typically focused on specific scenarios.…”

“…For example, Taouil et al [87] developed a methodology tailored for testing of memory-on-logic stacks and Deutsch et al [88] applied thermo-mechanical-stress-aware generation of test patterns for TSV-based 3D ICs. Offering a more holistic approach, Wang et al [84] enabled unified testing of wires, microbumps and TSVs for interposer stacks, with low overhead and compliance to the IEEE 1149.1 standard. Agrawal et al [89] proposed an efficient heuristic for testflow selection which can be applied for different configurations of 3D chip stacks; it is notably more efficient and qualitatively competitive to an optimal approach when stacking up to three dies.…”