Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs

Marescaux, Théodore; Bartic, Andrei; Verkest, D.; Vernalde, Serge; Lauwereins, Rudy

doi:10.1007/3-540-46117-5_82

Cited by 106 publications

(89 citation statements)

References 4 publications

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“…Wormhole routing [25] is a method to realize a communication infrastructure that circumvents the limitations of the approaches described above. Here, communication macros are used that span over one or more complete tiles, if the destination tile is not adjacent to the base region.…”

Section: A Communication Infrastructures Using Modified Link Macrosmentioning

confidence: 99%

“…Here, communication macros are used that span over one or more complete tiles, if the destination tile is not adjacent to the base region. These adapted link macros are referred to as wormhole macros or wormhole routing [25]. When the reconfigurable area comprises a large number of tiles, this approach consumes a considerable amount of routing resources, as can be seen in Fig.…”

Section: A Communication Infrastructures Using Modified Link Macrosmentioning

confidence: 99%

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Design Optimizations for Tiled Partially Reconfigurable Systems

Koester

Luk

Hagemeyer

et al. 2011

IEEE Trans. VLSI Syst.

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Abstract-In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static system, the design of a partially reconfigurable system requires additional design steps, such as partitioning the device resources into static and dynamic regions. We present the concept of tiled PR regions, which enables a flexible online-placement of PR modules. Dynamic reconfiguration requires a suitable communication infrastructure to interconnect the static and dynamic system components. We present an embedded communication macro, a communication infrastructure that interconnects PR modules in a tiled PR region. Efficient online-placement of PR modules depends not only on the placement algorithm, but also on design-time aspects such as the chosen synthesis regions of the PR modules. We propose a design method for selecting suitable synthesis regions for the PR modules aiming to optimize their placement at run-time.

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Section: A Communication Infrastructures Using Modified Link Macrosmentioning

confidence: 99%

Section: A Communication Infrastructures Using Modified Link Macrosmentioning

confidence: 99%

Design Optimizations for Tiled Partially Reconfigurable Systems

Koester

Luk

Hagemeyer

et al. 2011

IEEE Trans. VLSI Syst.

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“…Although most discussion of NoCs have been targeted on ASICs, NoCs are rather suitable for FPGAs with large wiring delay, and some researches have been reported recently [2]. For most NoCs on an FPGA, 2-D mesh has been utilized, since it is efficient in terms of area and power consumption compared with other topologies, and also it matches two-dimensional nature of the island-style FPGA interconnection.…”

Section: Introductionmentioning

confidence: 99%

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs

Wang

Matsutani

Koibuchi

et al. 2009

IEICE Trans. Inf. & Syst.

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SUMMARYThe regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.

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“…Reconfigurable computing systems have already shown the ability to greatly accelerate program execution, thereby providing a high-performance alternative to pure software-based implementations and a programmable alternative to expensive ASICs. The development of new architectural hardware/ software system concepts [3,10,13,19,24] by exploiting these powerful features of flexible and adaptive hardwareaccelerated coprocessors in combination with a design paradigm shift is an adequate approach to adapt to the market's requirements. Nevertheless the availability of the best superior reconfigurable architectures will not guarantee their success, if no sophisticated control and management mechanisms are provided by the system developers dealing with fault tolerance aspects and application scenarios with dynamically changing power/performance constraints.…”

Section: Introductionmentioning

confidence: 99%