Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices

Gaillardon, Pierre-Emmanuel; Clermidy, Fabien; O’Connor, Ian; Junchen, Liu

doi:10.1109/nanoarch.2009.5226348

Cited by 9 publications

(4 citation statements)

References 9 publications

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“…Since the interconnect topology is fixed and static, the choice of topology is made by the designer. In the context of matrix-based logic, the performance of the different topologies has been investigated in [23]. It has been shown that a Modified Omega topology has the best performance in terms of mapping efficiency.…”

Section: ) Mclusters: Adding a Logic Layermentioning

confidence: 99%

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells

Gaillardon

Tang

Kim

et al. 2015

IEEE Trans. VLSI Syst.

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Abstract-In this paper, we investigate the opportunity brought by controllable-polarity transistors to design efficient reconfigurable circuits. Controllable-polarity transistors are devices whose polarity can be electrostatically programmed to be either n-or p-type. Such devices are used to build ultrafine grain computation cells. These cells are arranged into regular matrices, called MClusters, with a fixed and incomplete interconnection pattern, employed to minimize the reconfigurable interconnection overhead. We subsequently use them into field-programmable gate arrays (FPGAs). To assess this architectural scheme in an efficient and objective manner, we present a complete benchmarking tool flow and focus on the packing algorithm developed to handle the architecture. We finally perform the evaluation with widely used benchmark circuits. Leveraging the ultrafine grain cells compactness from a system-level perspective, we show that FPGAs exploiting MClusters demonstrate average savings of 43% and 23% in area and delay, respectively, as compared with the CMOS lookup table FPGA counterpart at 22-nm technological node. IndexTerms-Controllable-polarity devices, fieldprogrammable gate arrays (FPGAs), packing tools, ultrafine grain logic, vertically stacked nanowires.

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Section: ) Mclusters: Adding a Logic Layermentioning

confidence: 99%

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells

Gaillardon

Tang

Kim

et al. 2015

IEEE Trans. VLSI Syst.

Self Cite

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“…But the improvement is limited due to the small portion of pass transistors in the routing structure. There are also studies on new reconfigurable circuit structures, such as CMOL [22] and CNTFET-based fine-grain cell matrices [23], with the aim of taking the place of FPGA. Lots of efforts are still needed to realize these revolutionary ideas in products.…”

Section: B Recent Work On Fpgas Using Emerging Technologiesmentioning

confidence: 99%

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

Cong

Xiao

2011

2011 IEEE/ACM International Symposium on Nanoscale Architectures

116

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Abstract-In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D diestacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA.

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“…In [4], a logic gate is presented, where the symmetric characteristic of ambipolar CNTFETs is exploited to build a single-transistor XOR gate. In [5], the authors construct configurable dynamic logic gates which can be configured by setting the polarity of the CNTFETs and in [6], an interconnection scheme is presented to implement complex circuits with these configurable gates. In [7], a novel static logic design methodology using ambipolar CNTFETs with controllable polarities is investigated, enabling the design of multi-level logic circuits.…”

Section: Introductionmentioning

confidence: 99%

Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications

Marchi¹,

Jamaa²,

Micheli³

2010

2010 IEEE/ACM International Symposium on Nanoscale Architectures

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Abstract-In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambipolar CNTFETs to design compact and efficient configurable gates. After evaluating a polarity-aware logic design for the configurable gates, we selected a number of gates with an And-Or-Inverter structure and produced a first comparison with existent medium-grained logic blocks, like the Actel ACT1 and 4-input LUTs [1]. Preliminary evaluation of our gates indicates improvements of around 47% over the ACT1 and of about 18× with respect to 4-input LUTs in terms of area×normalized delay.

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Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices

Cited by 9 publications

References 9 publications

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications

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