Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications

Marchi, Michele De; Jamaa, M. Haykel Ben; Micheli, Giovanni De

doi:10.1109/nanoarch.2010.5510923

Cited by 9 publications

(12 citation statements)

References 9 publications

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“…The fabricated devices show great potential in terms of logic design due to their intrinsic high logic expressive power. Recent works (7,9) demonstrate that logic design using ambipolar DG devices requires fewer resources than conventional CMOS. Moreover, implementation of sea-of-gate architectures with DG SiNW devices (10) can reduce fabrication costs by providing efficient circuit implementations and maintaining a high level of regularity in circuit layouts.…”

Section: Introductionmentioning

confidence: 99%

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

Marchi

Sacchetto

Frache

et al. 2012

2012 International Electron Devices Meeting

260

248

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We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show I on /I off > 10 6 and S 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.

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Section: Introductionmentioning

confidence: 99%

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

Marchi

Sacchetto

Frache

et al. 2012

2012 International Electron Devices Meeting

260

248

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“…We defined a gate library corresponding to the reconfigurable 4-input logic gate (Figure 4), which we used in order to synthesize the benchmark using the ABC tool [11]. It has been reported that gates similar to the used one have a high degree of reconfigurability [9]. The gate library was characterized using the presented DG-CNTFET compact model.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Secondly, we suggest using the input signals not only to make the calculation, but also to perform the configuration by providing the power supply signals as additional inputs, that we multiplex with the initial ones. Finally, we allow the permutation of the power supply of the logic cell, since the pull-up (PU) and pull-down (PD) networks of a DG-CNTFET can be designed with the same size [9]. The obtained novel reconfigurable cell is depicted in Figure 3 …”

Section: Every Clb Consists Of a Set Of N Basic Logic Elements (Bles)mentioning

confidence: 99%

FPGA Design with Double-Gate Carbon Nanotube Transistors

Jamaa¹,

Gaillardon²,

Fregonèse³

et al. 2011

ECS Trans.

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Double-gate carbon nanotube field effect transistors (DGCNTFETs) are novel devices showing an interesting property allowing to control the p-or n-type behavior during the device operation. This opens up the opportunity for novel design paradigms. Based on a compact physical model of these devices, we demonstrate the benefit of designing field-programmable gate arrays (FPGAs) using fine-grain DG-CNTFET logic blocs rather than traditional look-up tables and coarse-grain DG-CNTFET logic blocs. In particular, we show a reduction by 13% to 48% on average in terms of delay of FPGA benchmarks. IntroductionThe scaling down of complementary metal-oxide-semiconductor (CMOS) technology has led to the emergence of novel post-CMOS devices, such as carbon nanotubes (CNTs). One of the challenges of using CNT technology for building transistors is the chemical doping. Using undoped CNTs is possible, but it results in an ambipolar behavior of the carbon nanotube field effect transistors (CNTFETs), meaning that undoped CNTFETs conduct under both positive and negative gate bias. This issue is addressed using a second gate, which controls whether the device operates as p-or a n-type [1]. The polarity of double-gate (or dual-gate) CNTFETs (DG-CNTFETs) can be selected during operation time.This property offers the opportunity to design logic gates with reconfigurable devices, leading to more logic functions drawn on the same silicon area. We leverage this property by constructing a full reconfigurable logic system that is reminiscent of a fieldprogrammable gate array (FPGA). Reconfigurable circuits are gaining interest because of their low technology cost, fast design time and enhanced fault-tolerance compared to application-specific integrated circuits (ASICs) [2]. However, FPGAs necessitate a large number of configuration memories and have a higher cost in terms of area and power consumption compared to ASICs. Our approach to address these issues is to implement FPGAs using reconfigurable DG-CNTFET logic gates instead of look-up tables (LUTs) as basic logic elements (BLEs). Our BLEs require less configuration memory, and their design is area efficient.In order to assess the benefits of the proposed approach, we first build a family of basic logic elements with DG-CNTFETs, which we characterize using a compact model. , 34 (1) 1005-1010 (2011) 10.1149/1.3567706 We then evaluate the FPGA performance on a large application benchmark for different architecture scenarios. The same design flow is used with LUT-based FPGAs. We demonstrate that the proposed approach with fine-grain DG-CNTFET gates is 48% faster than coarse grains and 13% faster than LUTs. FPGAs with fine-grain DG-CNTFET gates have a cost in terms of area with respect to LUTs (10%), while they are 45% smaller than coarse-grain DG-CNTFET gates. ECS TransactionsThe paper is organized as follows. We first survey previous works dealing with DG-CNTFET technology. Then we introduce a compact physical model for the considered devices. Subsequently, we introduce the design of re...

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“…We limited our analysis to medium-grained cells, including at most three elements (transistors or transmission gates) in the PU and PD networks, as these allow us to highlight the structural advantage given by configurable polarity transistors [7].…”

Section: Ambipolar Cntfet Regular Fabric Designmentioning

confidence: 99%

“…In [7], the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic was investigated. Various medium-grained logic gates were used as configurable gates to perform technology mapping on a set of benchmark circuits.…”

Section: Introductionmentioning

confidence: 99%

Synthesis of regular computational fabrics with ambipolar CNTFET technology

Marchi

Bobba

Jamaa

et al. 2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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Abstract-In this paper, we report on a physical design of regular fabrics with ambipolar CNTFET devices. Three mediumgrain size cells, built with ambipolar CNTFETs with in-field controllable polarities are evaluated. We designed regular layouts using these cells using 32nm technology rules and we performed technology mapping and routing of a set of benchmark circuits. CNTFET-based cells were then compared with an existent configurable cell of similar grain size, the Actel ACT1 logic brick, simulated with a 32nm MOSFET model. We obtained delays about 2× better than those obtained with ACT1 after normalization to the intrinsic technology delay. After technology mapping and routing steps, we report performances about 8× better in terms of area × normalized delay for the CNTFETbased cells over the Actel ACT1 cell.

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Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications

Cited by 9 publications

References 9 publications

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

FPGA Design with Double-Gate Carbon Nanotube Transistors

Synthesis of regular computational fabrics with ambipolar CNTFET technology

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