a) Figure I. The analog FLL of (I], (a), and the digitally-assisted FLL, (b).(b) '------1 II. SYSTEM-LEVEL DESIGN In Fig. 1a, a simplified block diagram of an analog FLL of [1] is shown. The YCO drives the ETF as well as a synchronous demodulator, which detects the phase of the ETF's output signal. The output of the synchronous demodulator is then integrated by an analog filter, which drives the YCO. The loop locks when the demodulator's DC output is zero, corresponding to a YCO frequency fvco = .190at which the phase shift of the ETF's near-sinusoidal output is about 90°. The FLL's phase-frequency characteristic is thus locked to that of the ETF.A block diagram of the proposed digitally-assisted electrothermal FLL is shown in Fig. 1b. Besides a YCO and an ETF, it consists of a phase domain M: modulator (PDM:M), a DAC, and a digital filter. The YCO drives the ETF, whose phase shift is then digitized by the PDM:M [5,6]. The latter's bitstream output is then compared with a phase reference of 90°, and the resulting error signal is then Hz were achieved with the help of a large (1 IlF) off-chip capacitor. In the digitally-assisted FLL described here, the noise bandwidth is defined by a digital filter, resulting in a solution that is more amenable to CMOS integration.In the next section, the system-level design of a digitallyassisted electrothermal FLL is described. Section III provides an overview of the circuit, while the measurement results are presented in section IY. The paper ends with conclusions.