Interface states in cycled hot electron injection program∕hot hole erase silicon–oxide-nitride–oxide–silicon memories

Daniel, Ramiz; Shaham-Diamand, Yossi; Roizin, Yakov

doi:10.1063/1.1839289

Cited by 10 publications

(4 citation statements)

References 4 publications

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“…The FN hole injection could provide an erase mechanism alternative to the currently used "hot" holes, which are the principal cause of the BOX degradation in NROM cells. [3][4][5] Moreover, the FN hole injection could enable a refresh operation of the memory cell. 15 Aluminum oxide, Al 2 O 3 , ͑k =7-10͒ ͑Ref.…”

mentioning

confidence: 99%

Si O 2 ∕ Si 3 N 4 ∕ Al 2 O 3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing

Lisiansky

Heiman

Kovler

et al. 2006

Applied Physics Letters

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Effects of interfaces and thermal annealing on the electrical performance of the SiO 2 /Si 3 N 4 /Al 2 O 3 ͑ONA͒ stacks in nonvolatile memory devices were investigated. The results demonstrated the principal role of Si 3 N 4 /Al 2 O 3 and Al 2 O 3 /metal-gate interfaces in controlling charge retention properties of memory cells. Memory devices that employ both electron and hole trappings were fabricated using a controlled oxidation of nitride surface prior to the Al 2 O 3 growth, a high-temperature annealing of the ONA stack in the N 2 +O 2 atmosphere, and a metal gate electrode having a high work function ͑Pt͒. These devices exhibited electrical performance superior to that of their existing SiO 2 /Si 3 N 4 / SiO 2 analogs.

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mentioning

confidence: 99%

Si O 2 ∕ Si 3 N 4 ∕ Al 2 O 3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing

Lisiansky

Heiman

Kovler

et al. 2006

Applied Physics Letters

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“…The percentage of increase in the maximum I CP during NOI erasing shows that hot holes induce more serious interface degradation than hot electrons do during the P/E cycling of NOI devices. 29,30) On the basis of the two-step N it assumption for the charge pumping analysis reported in Ref. 12, the local V th distribution is determined and shown in Fig.…”

Section: Erasing Charge Injection Profilingmentioning

confidence: 99%

Comprehensive study of hole injection in non-overlapped implantation n-type MOSFETs

Jeng¹,

Fan²,

Peng³

et al. 2014

Jpn. J. Appl. Phys.

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The promising use of non-overlapped implantation (NOI) n-type MOSFETs as nonvolatile memory (NVM) devices has received considerable interest owing to their simple device structure and compatibility with logic CMOS processing. In NOI n-type MOSFETs, the charge distribution by channel hot electron injection (CHEI) programming markedly differs from that in other charge trapping devices in terms of electron injection distribution. In this study, hot hole injection (HHI) in NOI NVM devices is investigated using Technology Computer Aided Design (TCAD) simulations, measured program/erase speeds, and charge pumping (CP) techniques. Furthermore, HHI efficiency is theoretically deduced and compared with that of silicon-oxide-nitride-oxide-silicon (SONOS) devices. Similar to the results for SONOS device, the lateral fields by V D biases significantly enhance HHI for erasing NOI devices. However, preprogrammed electrons are also dominant in erasing NOI devices. On the basis of the CP results, the hole distribution by HHI in NOI NVM devices strongly correlates with the distribution of preprogrammed electrons.

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“…The poly-TFTs with oxide-nitride-oxide (ONO) dielectric studied in this letter can act not only as display backplane electronics, including the in-pixel switches and the peripheral circuits, but also as a nonvolatile memory device. Because functional devices are frequently operated in the OFF-state (V g < 0, V d > 0), the degradation behavior in OFF-state stress is worth studying in detail for reliability issues [4], [5]. Furthermore, the OFF-state operation can induce band-to-band hothole injection, which is utilized for erase in a nonvolatile memory device.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation

Chen

Chang

Chen

et al. 2010

IEEE Electron Device Lett.

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This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxidenitride-oxide-silicon structure under OFF-state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant ON-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I-V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hothole injection, the degradation is mainly affected by the lateral electrical field over a critical point.

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Interface states in cycled hot electron injection program∕hot hole erase silicon–oxide-nitride–oxide–silicon memories

Cited by 10 publications

References 4 publications

Si O 2 ∕ Si 3 N 4 ∕ Al 2 O 3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing

Si O 2 ∕ Si 3 N 4 ∕ Al 2 O 3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing

Comprehensive study of hole injection in non-overlapped implantation n-type MOSFETs

Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation

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