Interface traps responsible for negative bias temperature instability in a nitrided submicron metal-oxide-semiconductor field effect transistor

Yonamoto, Yoshiki; Akamatsu, Naotoshi

doi:10.1063/1.3559223

Cited by 7 publications

(3 citation statements)

References 16 publications

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“…Similar experimental results are also shown in Yonamoto et al work, in which they conclude that NBTI is due to an increase of the P b1 -center rather than the P b0 -center [17]. To summarize, the NBTI characteristics and mechanism in the SiO 2 /SiON are reviewed.…”

Section: Reliability Issue Of the Sion Gate Stacksupporting

confidence: 76%

“…the SiON is used to replace the SiO 2 in order to suppress the gate leakage and boron penetration. Many experimental results have shown that the presence of nitrogen in the gate oxide has substantially worsens the BTI performance [8,9,[16][17][18][19][20][21][22]. Kimizuka et al are those pioneers that conducting the NBTI study on the SiON device [9,23].…”

Section: Bias Temperature Reliability Of the Advanced Gate Stackmentioning

confidence: 99%

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Atomistic simulation study of high-?? oxide defects for understanding gate stack and RRAM reliability

Gu¹

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Bias temperature instability (BTI) is widely recognized as a critical reliability issue for the state-of-the-art complementary metal-oxide-semiconductor (CMOS) device. Generally, BTI is result from a progressive building up of the interface states and bulk oxide charges under the combining effect of the gate voltage and an elevated temperature. These charged defects will shift the threshold voltage (V t) of the metaloxide-semiconductor field-effect transistor (MOSFET) and degrade the inversion charge mobility, reducing the device driving current. Worse case, when the shift of V t exceeds the design tolerance, functional failure of integrated circuits may result. Previous studies of the NBTI on the SiON gated device show that the threshold voltage degradation is typically characterized by a much weaker dependence on the stress time and temperature as compared to that of the SiO 2 counterpart. Moreover, in a recent NBTI study, Ang et al. reveals the presence of deep-level hole traps (DLHTs) after negative-bias temperature stressing. Their experimental results show that the hole traps have energy states above the Si Fermi potential, which enable them have the ability to retain the positive charges for a very long time after the negative gate biasing. However an unambiguous understanding of the role of nitrogen on the DLHTs generation is still not available. Therefore, in this work, we investigate the impact of nitrogen on the trap level generation via first-principles modeling and simulation. Our results show that the coordination of the neighboring nitrogen atom plays a paramount role on the structural relaxation of V O following the capture of a hole. In particular, a twofold coordinated nitrogen atom is shown to induce very significant structural relaxation of V O. The resultant trapped-hole site has a very deep charge transition level Abstract VIII in the SiO 2 band gap (DLHTs). On the other hand, in the absence of the nitrogen atom or if the neighboring nitrogen atom is threefold coordinated (e.g., the dangling nitrogen bond is terminated by a hydrogen atom). The resultant trapped-hole site would have a much shallower charge transition level. This set of simulation results show a clear correlation between nitrogen in the gate oxide and the DLHT generation by negative-bias temperature stress. Besides, in Ang's work, a broad energy distribution of stress induced positive trap states across over the band gap were detected, whereas knowledge on how the neighboring nitrogen atoms affect the defect levels in the SiON is quite limited. Hence, in the subsequent modeling and simulation work, we modeled various oxide defects with different nitrogen configurations in the SiON gate stack. Our simulation results from these models show a widespread of the defects levels within the SiON gap due to the different dynamics of these defect morphors. Distinctive relaxation characteristics of deep-level hole traps, as compared to those of the interface states, are also observed. As the scaling of the transistors continuously moves ...

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Section: Reliability Issue Of the Sion Gate Stacksupporting

confidence: 76%

Section: Bias Temperature Reliability Of the Advanced Gate Stackmentioning

confidence: 99%

Atomistic simulation study of high-?? oxide defects for understanding gate stack and RRAM reliability

Gu¹

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“…[9,10] More attention has been paid to this problem in recent years. [11][12][13] However, in spite of the intensive studies on the recovery issue, the physical mechanism is still far from being fully understood. In this paper, we study the recovery of NBTI systemically under different conditions in the 90-nm PMOSFETs, explain the various recovery phenomena, and find the possible processes of the recovery.…”

Section: Introductionmentioning

confidence: 99%

Recovery of PMOSFET NBTI under different conditions

et al. 2015

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Negative bias temperature instability (NBTI) has become a serious reliability issue, and the interface traps and oxide charges play an important role in the degradation process. In this paper, we study the recovery of NBTI systemically under different conditions in the P-type metal–oxide–semiconductor field effect transistor (PMOSFET), explain the various recovery phenomena, and find the possible processes of the recovery.

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Recovery behavior in negative bias temperature instability

Yonamoto

2014

Microelectronics Reliability

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Interface traps responsible for negative bias temperature instability in a nitrided submicron metal-oxide-semiconductor field effect transistor

Cited by 7 publications

References 16 publications

Atomistic simulation study of high-?? oxide defects for understanding gate stack and RRAM reliability

Atomistic simulation study of high-?? oxide defects for understanding gate stack and RRAM reliability

Recovery of PMOSFET NBTI under different conditions

Recovery behavior in negative bias temperature instability

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