Interfacial adhesion study for low-k interconnects in flip-chip packages

Miller, Marisa E.; Ho, Paul S.

doi:10.1109/ectc.2000.853306

Cited by 5 publications

(2 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The Copper/Low-K interfacial strength and assembly process induced Low-K interfacial crack driven force had been addressed and studied [1]. The thermal stress and debond characteristics of Cu/Low-K structure in a flip-chip package was also investigated experimentally and analyzed by finite element method [2,3]. Low-K flip-chip underfill characterization had been studied [4] and lower Tg underfill had been shown to achieve flip-chip package reliability requirements without Low-K IMD failure.…”

Section: Introductionmentioning

confidence: 99%

Low-K Flip Chip Board Level Reliability on 65nm Technology

Tsao

Kiang

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

View full text Add to dashboard Cite

Higher coefficient of thermal expansion (CTE) of printed wiring board (PWB), compared with that of silicon chip, makes the impact on thermally induced stress in IC Chip by PWB a great concern for IC with Low-K inter-metaldielectric (IMD) product reliability. To characterize and validate the 65nm technology flip-chip (FC) package reliability, 20x20mm2 test chip were assembled in a 42.5x42.5 mm2 flip-chip packages for board level reliability tests, mainly temperature cycling test, mechanical bending test and mechanical shock/vibration tests. The test results showed that no Low-K and bump joint failure was found in shock/vibration test.

show abstract

Section: Introductionmentioning

confidence: 99%

Low-K Flip Chip Board Level Reliability on 65nm Technology

Tsao

Kiang

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

View full text Add to dashboard Cite

show abstract

“…The CopperiLow-k interfacial strength and assembly process induced Low-k interfacial crack driven force had been addressed and studied [I]. The thermal stress and debond characteristics of CdSiLK stmctnre in a flip-chip package was investigated experimentally and analyzed by finite element method [2,3]. Assembly wirebonding impacts on chip Low-K layer integrity had also been investigated [4].…”

Section: Introductionmentioning

confidence: 99%

Cavity-down thermal-enhanced package reliability evaluation for low-k dielectric/Cu interconnects IC

Tsao

Huang

Lin

et al.

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)

View full text Add to dashboard Cite

It has been well recognized that IC packaging materials have a great impact on the IC chip integrity of chips fabricated by low dielectric constant inter-metal-dielectric (Low-k IMD) materials. To understand the effect of the package process and material in the cavity-down thermalenhanced BGA package on Low-k IMD chip integrity, packages characterization by both encapsulation process and transfer-mold process was performed. The package samples were built with two different encapsulants and two different molding compounds.The test result showed that encapsulants induced chip comer defects due to the high shrinkage rate and free-body movement of the encapsulant during curing process. The defects led to package early reliability fail with Low-k IMD delamination failure mode. The transfer-mold type cavity-down BGA with low coefficient of thermal expansion (CTE) compound yielded most promising package reliability test results to realize the cavity-down package solution for Low-k chip.

show abstract

Interfacial adhesion study for copper/SiLK interconnects in flip-chip packages

Miller

Ho²

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)

View full text Add to dashboard Cite

Interfacial adhesion study for low-k interconnects in flip-chip packages

Cited by 5 publications

References 16 publications

Low-K Flip Chip Board Level Reliability on 65nm Technology

Low-K Flip Chip Board Level Reliability on 65nm Technology

Cavity-down thermal-enhanced package reliability evaluation for low-k dielectric/Cu interconnects IC

Interfacial adhesion study for copper/SiLK interconnects in flip-chip packages

Contact Info

Product

Resources

About