Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications

Raffel, Yannick; Thunder, Sunanda; Lederer, Maximilian; Olivo, Ricardo; Hoffmann, R.; Pirro, L.; Beyer, Sven; Chohan, Talha; Huang, Po-Tsang; De, Sourav; Kämpfe, Thomas; Seidel, Konrad; Heitman, Johannes

doi:10.1109/icicdt56182.2022.9933119

Cited by 10 publications

(8 citation statements)

References 20 publications

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“…However, a higher value of remanent polarization also enabled the possibility of downsizing the thickness of the oxide layer. Therefore, the theoretical limit on the scaling is relaxed for realizing FeFET memory devices [10][11][12][13][14][15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Neuromorphic Computing with 28nm High-K-Metal Gate Ferroelectric Field Effect Transistors Based Artificial Synapses

Raffel¹,

Müller²,

Thunder³

et al. 2023

Preprint

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This paper presents a comprehensive overview of 28 nm high-k-metal gate-based ferroelectric field effect transistor devices for synaptic applications. The device under test was fabricated on 300mm wafers at GlobalFoundries. The fabricated devices demonstrate 103 WRITE-endurance cycles and 104 seconds of data-retention capability at 85°C. We have also assessed the FeFET-based crossbar array’s performance in system-level applications. By simulating the FeFET crossbar array for neuromorphic applications, the system performance was assessed. For datasets from the National Institute of Standards and Technology (MNIST), the crossbar array achieved software-comparable inference accuracy of about 97% using multilayer perceptron (MLP) neural networks.

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Section: Introductionmentioning

confidence: 99%

Neuromorphic Computing with 28nm High-K-Metal Gate Ferroelectric Field Effect Transistors Based Artificial Synapses

Raffel¹,

Müller²,

Thunder³

et al. 2023

Preprint

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“…The presence of charge traps at the Ferroelectric /interlayer interface and within the Ferroelectric film can lead to asymmetrical conductive response and large deviceto-device variations [20]- [22]. Abundant efforts have been made to minimize the effects of such non-idealities both from the devices and from the circuits perspective [23]- [28].…”

Section: Introductionmentioning

confidence: 99%

Design of Variation-Tolerant 1F-1T Memory Array for Neuromorphic Computing

Rana¹,

Thunder²,

Müller³

et al. 2023

Preprint

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This letter proposes a memory cell, denoted by 1F-1T, consisting of a ferroelectric field-effect transistor (Fe-FET) cascoded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET, denoted by 1F. We have fabricated 28nm high-k-meta-gate (HKMG) based FeFETs, and the experimental data is used to model and simulate single-cell and memory arrays. The simulation shows significant improvement in bit-line (BL) current (IBL ) variation for 1F-1T memory array. Finally, the system-level neuromorphic simulation with 1F-1T synapses shows an inference accuracy of 97.6% for MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.

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“…Among many emerging memory technologies like resistive random access memory (ReRAM) − and phase change memory (PCM), − ferroelectric field effect transistors (FeFETs) seem to be the most promising ones. The pronunciation of ferroelectricity in a single-layer thin film of hafnium oxide (HfO 2 ), fast switching, high on-current ( I ON ) to off-current ( I OFF ) ratio , excellent linearity in synaptic weight updates, bidirectional operation, and good endurance are the key technological factors that make FeFET superior to other methods. ,− ,, However, the primary bottleneck in implementing the FeFET-based computing system lies in the intrinsic stochasticity owing to the polycrystalline nature of HfO 2 -based ferroelectric thin film, as well as inherent defect sites that may capture electrons or holes from the channel side (CS) or gate side (GS). − Numerous efforts have been made to reduce the impacts of such nonidealities from the device process, and a circuit point of view. − ,, Previously, it has been reported how the quality of the interface and the READ -Voltage play a pivotal role in the performance of FeFETs, especially for low-frequency noise response, retention, and endurance. ,,,,− In this work, we aim to maximize the reliability and performance of FeFETs by adopting a synergistic approach of READ -voltage optimization and interfacial-layer engineering.…”

Section: Introductionmentioning

confidence: 99%

“… 34 − 39 , 23 , 25 Previously, it has been reported how the quality of the interface and the READ -Voltage play a pivotal role in the performance of FeFETs, especially for low-frequency noise response, retention, and endurance. 40 , 41 , 25 , 21 , 42 − 44 In this work, we aim to maximize the reliability and performance of FeFETs by adopting a synergistic approach of READ -voltage optimization and interfacial-layer engineering.…”

Section: Introductionmentioning

confidence: 99%

Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO₂-Based FeFETs for In-Memory-Computing Applications

Raffel

Lederer

et al. 2022

ACS Appl. Electron. Mater.

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This article reports an improvement in the performance of the hafnium oxide-based (HfO2) ferroelectric field-effect transistors (FeFET) achieved by a synergistic approach of interfacial layer (IL) engineering and READ-voltage optimization. FeFET devices with silicon dioxide (SiO2) and silicon oxynitride (SiON) as IL were fabricated and characterized. Although the FeFETs with SiO2 interfaces demonstrated better low-frequency characteristics compared to the FeFETs with SiON interfaces, the latter demonstrated better WRITE endurance and retention. Finally, the neuromorphic simulation was conducted to evaluate the performance of FeFETs with SiO2 and SiON IL as synaptic devices. We observed that the WRITE endurance in both types of FeFETs was insufficient ( < 10 8 ) to carry out online neural network training. Therefore, we consider an inference-only operation with offline neural network training. The system-level simulation reveals that the impact of systematic degradation via retention degradation is much more significant for inference-only operation than low-frequency noise. The neural network with FeFETs based on SiON IL in the synaptic core shows 96% accuracy for the inference operation on the handwritten digit from the Modified National Institute of Standards and Technology (MNIST) data set in the presence of flicker noise and retention degradation, which is only a 2.5% deviation from the software baseline.

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Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications

Cited by 10 publications

References 20 publications

Neuromorphic Computing with 28nm High-K-Metal Gate Ferroelectric Field Effect Transistors Based Artificial Synapses

Neuromorphic Computing with 28nm High-K-Metal Gate Ferroelectric Field Effect Transistors Based Artificial Synapses

Design of Variation-Tolerant 1F-1T Memory Array for Neuromorphic Computing

Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO₂-Based FeFETs for In-Memory-Computing Applications

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Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications

Cited by 10 publications

References 20 publications

Neuromorphic Computing with 28nm High-K-Metal Gate Ferroelectric Field Effect Transistors Based Artificial Synapses

Neuromorphic Computing with 28nm High-K-Metal Gate Ferroelectric Field Effect Transistors Based Artificial Synapses

Design of Variation-Tolerant 1F-1T Memory Array for Neuromorphic Computing

Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications

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Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO₂-Based FeFETs for In-Memory-Computing Applications