Interfacial properties of metal–insulator–semiconductor capacitors on GaAs(110)

Abstract

GaAs metal insulator semiconductor capacitors and high transconductance metal insulator semiconductor field effect transistorsPassivation of both cleaved GaAs͑110͒ facets and wafers ͑both n and p types͒ was performed with different surface treatments including HF-etch of native oxide, passivation with an ammonium sulfide solution, passivation with hydrogen polysulfide, and passivation with a Si/S, Ge/S, or Si/Ge/S interface control layer. The interface state density was measured with capacitance-voltage ͑CV͒ measurements of metal-insulator-semiconductor capacitors fabricated on the passivated surfaces using remote plasma deposited silicon nitride as gate insulator. The interface structures of the capacitors were analyzed by x-ray absorption near-edge structure spectroscopy and x-ray photoemission spectroscopy. It was found that, while the passivation procedures with the sulfur compounds or a Si/S interface control layer did improve the CV data when compared with the HF oxide etch, the Si/Ge/S multilayer passivation technique led to the best CV results. By comparing the quasistatic and high frequency ͑1 MHz͒ CV data, we found that the minimum interface state density of the fabricated capacitors was about 10 12 eV Ϫ1 cm Ϫ2 . The results were compared with those obtained from GaAs͑100͒ and the difference was addressed with respect to the surface geometry and the electronic structures.

Electrical characteristics of Ge/GeOx(N)/HfO2 gate stacks

“…3(a). A frequencydispersion in the capacitance is observed, in accumulation, depletion and inversion, indicating the presence of a density of interface defects $10 13 cm 2 [10], which is the result of a poor Ge/GeO x interface passivation. Table 1 Thickness and N content of the GeO x (N) interfacial layers, obtained from X-ray photoelectron spectroscopy measurements, for the HF-last cleaned Ge surfaces and the different NH 3 As shown in Fig.…”

Minority-carrier characteristics of SiNx/GaAs metal–insulator–semiconductor structures with Si/Ge interlayers

“…[1][2][3][4][5][6][7][8][9][10][11][12] As observed recently, this is achieved fairly well by utilizing epitaxial Si and/or Si/Ge interlayers [2][3][4][5][6][7][8][9] or by employing Ga 2 O 3 on GaAs. 10 A density of interface trap states (D it )ϳmid-10 10 eV Ϫ1 cm Ϫ2 was obtained from Si 3 N 4 /Si/GaAs(001) structures with a few monolayers of an interfacial Si layer.…”

“…7,8 This trap density may be considered low enough to yield an unpinned surface Fermi level in GaAs MIS structures. In addition, the incorporation of a Si/Ge interface layer 6,9 and/or a strained Si/ InGaAs layer 11 between GaAs and the insulator has improved the performance of depletion mode GaAs MISFETs. Encouraged by our recent results on GaAs MIS structures with Si and/or Si/Ge interlayers, [7][8][9]11,12 an investigation into the minority-carrier characteristics of the SiN x /GaAs MIS interface using Si and Si/Ge interface layers was undertaken.…”

Fermi-Level Unpinning Using a Ge-Passivated Metal–Interlayer–Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors

“…However, previous experiments on MIS structures have not efficiently suppressed Fermi-level pinning because both the density of the MIGS (DMIGS) and the interface state trap density (Dit) of the semiconductor surface are important factors in III-V semiconductors due to their wider band gap [9]. Especially, the DMIGS of GaAs is about 3 × 10 14 cm -2 ·eV -1 [9] and the Dit at the GaAs surface is over 10 13 cm -2 ·eV -1 [10] which is comparable to the DMIGS.…”