Interfacial stress characterization for stress-induced voiding in Cu/low-k interconnects

Wang, R.C.J.; Chen, L.D.; Yen, Pi-Hsia; Lin, Shi-Chen; Chiu, Catherine; Wu, Kaijie; Chang-Liao, K. S.

doi:10.1109/ipfa.2005.1469138

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…In accordance with former report, the SIV failure mode of voiding at via bottom is associated with the geometry of upper metal [2]. Hence, in order to study microstructure effect, the width of upper metal in this model is defaulted to be 20um and maximum z-axis stress component at Cu via bottom is determined as an indication to evaluate via SIV [6].…”

Section: Siv Simulation Modellingmentioning

confidence: 71%

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A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

Wang

Lee

Chen

et al. 2006

Microelectronics Reliability

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Section: Siv Simulation Modellingmentioning

confidence: 71%

“…Several failure mechanism of SIV were discussed and finite element analysis become an indispensable tool to study and characterize stress component in copper interconnect [4]. In addition, it had been reported that Cu/low-k interfacial stress was highly correlated with sizes of copper macro-geometries and Cu via voiding sites [6].…”

Section: Introductionmentioning

confidence: 99%

A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

Wang

Lee

Chen

et al. 2006

Microelectronics Reliability

Self Cite

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Test structure to evaluate the impact of neighboring features on stress of metal interconnects

Smith

Shroff

2014

2014 International Conference on Microelectronic Test Structures (ICMTS)

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The stress-inducing effects of neighboring metal interconnect features were studied using novel stressmigration test structures with various layouts of perpendicular neighboring combs. The structures with narrow widths showed no change in stressmigration performance, with or without near-neighbor structures. However, structures built with wider lines showed up to 3X worse stressmigration performance when perpendicular combs were present nearby, essentially independent of the spacing to the combs. Thus, near neighbor metal features were shown to be capable of degrading SM performance in some lines. Keywords-stress; voiding; test structure I. ABSTRACTPublications in MEMS technologies report the use of thermal expansion to cause deflection of a free-floating needle [1][2][3][4][5][6][7]. This can be used to measure the stress applied by neighboring (and connected) features. Free-floating shapes don't exist in a typical CMOS technology but the stress applied by neighboring structures is still present. As stress can modulate the reliability of the interconnects [8-12], understanding the impact of any neighboring features is important.This study used a novel test structure to apply stress to a via chain using comb features that had no electrical connection. Measurements of resistance shift due to stress-induced voiding (SIV), also known as stressmigration (SM), were used as a metric for that stress. Neighboring combs with various layouts were investigated, in order to test the hypothesis that perpendicular "aggressor" metal lines would apply stress to the device under test (DUT), resulting in worse SM performance. Furthermore, the effect should decrease with the distance between the aggressor lines and the DUT. SM is generally determined by measuring the initial resistance of a DUT, baking it at an elevated temperature (e.g., 150-225°C) for a long time (e.g., 1000 hrs) with no current flow, and then measuring its resistance again. The shift in resistance is its SM performance. In such a high-temperature environment, vacancies in metal interconnects can migrate and accumulate at the regions of stress discontinuities (e.g., vias), resulting in higher resistance. Therefore, a lower resistance shift after baking indicates better SM robustness in the sample.

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A Study on Effect of Top and Bottom Metal Plates on Stress Induced Voiding of Nose Type Single Via Structure

Kuppar

Zeng

et al. 2018

2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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Interfacial stress characterization for stress-induced voiding in Cu/low-k interconnects

Cited by 3 publications

References 10 publications

A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

Test structure to evaluate the impact of neighboring features on stress of metal interconnects

A Study on Effect of Top and Bottom Metal Plates on Stress Induced Voiding of Nose Type Single Via Structure

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