Interfacial tunneling barrier heights in triple-layer dielectrics

Baunach, R.; Spitzer, A.

doi:10.1016/0169-4332(87)90091-2

Cited by 16 publications

(2 citation statements)

References 7 publications

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“…Consequently, a large amount of work has been done for films in the range of 5-10 nm. [11][12][13][14][15][16][17] However, little is known about the current transport in stacked ON and ONO structures, when the oxide equivalent thicknesses of these dielectrics are reduced in the direct tunneling region extending to 1.5-2.0 nm.…”

Section: Introductionmentioning

confidence: 99%

Tunneling currents through ultrathin oxide/nitride dual layer gate dielectrics for advanced microelectronic devices

Yang

Niimi

Lucovsky

1998

Journal of Applied Physics

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Direct and Fowler-Nordheim tunneling currents through oxide and dual layer silicon oxide-silicon nitride dielectrics are investigated for substrate and gate injection. The calculations include depletion effects in the heavily doped (n ϩ) polysilicon gate electrodes as well as quantization effects in the less heavily doped n-type substrates. The Wentzel-Kramers-Brillouin ͑WKB͒ effective mass approximation has been compared with exact calculations for the tunneling probability, and based on these comparisons it has been found that the WKB approximation is adequate for single layer dielectrics, but is not for the dual layer dielectrics that are the focus of this article. Using exact tunneling transmission calculations, current-voltage (I-V) characteristics for ultrathin single layer oxides with different thicknesses ͑1.4, 2.0, and 2.3 nm͒ have been shown to agree well with recently reported experiments. Extensions of this approach demonstrate that direct tunneling currents in oxide/nitride structures with oxide equivalent thickness of 1.5 and 2.0 nm can be significantly lower than through single layer oxides of the same respective thickness.

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Section: Introductionmentioning

confidence: 99%

Tunneling currents through ultrathin oxide/nitride dual layer gate dielectrics for advanced microelectronic devices

Yang

Niimi

Lucovsky

1998

Journal of Applied Physics

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“…It is well-known that silicon nitride has a high trap density and that the charge trapping behavior depends on the processing chemistry (11,12). The detrapping process is determined by the potential barrier of the nitride-oxide inter- face which can be more than l eV larger than corresponding barriers at the interface Si-SiO2 (13). Therefore the amount of trapped electrons can reach values up to some 10 TM electrons/cm 2 in saturation with the centroid of the trapped charge positioned in the middle of the nitride layer (14).…”

Section: Comparison Of Double and Triple Layer Dielectricsmentioning

confidence: 99%

Reliability of 10 nm Stacked Insulator on Polycrystalline Silicon in Planar and Trench Capacitors

Vollertsen

Thanh

Sichart

et al. 1990

J. Electrochem. Soc.

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The reliability of three types of stacked insulating films (ONO, ON, NO) with thicknesses of 10 nm and below deposited on highly doped polysilicon are compared. It is shown that the doping process of the underlaying polysilicon plays an important role in the dielectric breakdown behavior. Evaluation of I-E characteristics from voltage ramp measurements demonstrates the influence of top and bottom oxide thickness. Under NO double layers generally a native oxide is found. This leads to similar reliability results as found for triple layers. Real double layers (ON) without any potential barrier at the top electrode show significantly shorter lifetimes at positive gate voltage. Hence the native oxide between bottom electrode and nitride is not negligible. Extrapolations of the data measured by the constant voltage method on planar and trench capacitors indicate that the investigated ultrathin multilayer films on polysilicon show promise as dielectrics in storage capacitors of future DRAMs.

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Charge Trap Spectroscopy in Single and Multiple Layer Dielectrics

Fitting

Magdanz

Mehnert

et al. 1990

phys. stat. sol. (a)

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Charges in single and multiple dielectric layer systems can be detected by measuring their field strengths towards the substrate and the surface. Therefore a method combination of Kelvin‐probe and capacity voltage spectroscopy (C–U) is applied allowing charge measurement as well as location of its mean depth. Electron beam charge carrier injection and secondary electron field emission (SEFE) spectroscopy together with Kelvin‐C–U mapping provide electron and hole trap parameters in SiO2 and Si3N4/SiO2 multiple layer structures.

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Interfacial tunneling barrier heights in triple-layer dielectrics

Cited by 16 publications

References 7 publications

Tunneling currents through ultrathin oxide/nitride dual layer gate dielectrics for advanced microelectronic devices

Tunneling currents through ultrathin oxide/nitride dual layer gate dielectrics for advanced microelectronic devices

Reliability of 10 nm Stacked Insulator on Polycrystalline Silicon in Planar and Trench Capacitors

Charge Trap Spectroscopy in Single and Multiple Layer Dielectrics

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