2004
DOI: 10.1109/tdmr.2004.831989
|View full text |Cite
|
Sign up to set email alerts
|

Interlevel Dielectric Failures in Copper/Low-k Structures

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
18
0

Year Published

2005
2005
2020
2020

Publication Types

Select...
5
3
2

Relationship

0
10

Authors

Journals

citations
Cited by 42 publications
(18 citation statements)
references
References 12 publications
0
18
0
Order By: Relevance
“…5 During plasma processing, both ion bombardment and vacuum ultraviolet (VUV) irradiation can occur. [6][7][8][9] Defect states (and subsequent trapped charge) generated by both VUV irradiation and charged-particle bombardment of low-k dielectrics have been shown to adversely affect the capacitance, 10-12 breakdown voltage, 13 and leakage currents 14,15 in addition to causing chemical and structural changes 16 in organosilicate dielectrics. In this letter, it is shown that both photons and charged particles emitted during plasma processing have a deleterious effect on the time to dielectric breakdown, i.e., the dielectric lifetime.…”
mentioning
confidence: 99%
“…5 During plasma processing, both ion bombardment and vacuum ultraviolet (VUV) irradiation can occur. [6][7][8][9] Defect states (and subsequent trapped charge) generated by both VUV irradiation and charged-particle bombardment of low-k dielectrics have been shown to adversely affect the capacitance, 10-12 breakdown voltage, 13 and leakage currents 14,15 in addition to causing chemical and structural changes 16 in organosilicate dielectrics. In this letter, it is shown that both photons and charged particles emitted during plasma processing have a deleterious effect on the time to dielectric breakdown, i.e., the dielectric lifetime.…”
mentioning
confidence: 99%
“…7 (b). Most of the failure modes for IMD reported suggest that Cu diffuses along the weak chemical-mechanical polishing (CMP) interfaces to cause leakage and eventually cracks in the cap layer and/or diffusion barrier [10]. Since the interface between SiOC and capping layer is vulnerable to being damaged during the dielectric etching, CMP, and plasma pretreatment, it is quite common to have the dielectric breakdown failure to be observed at the interface such as IMD and the capping layer [11].…”
Section: Resultsmentioning
confidence: 99%
“…3 Charge accumulation can lead to increased leakage currents and shortened lifetimes of microelectronic devices. 4,5 Photon bombardment, as mentioned above, can cause charge accumulation through several processes. It is seen that electrons can be photoemitted into the vacuum region, photoinjected from the silicon substrate, or become sufficiently energetic to move within the dielectric due to photoabsorption and/or photoconduction.…”
Section: Charge Accumulation and Charge-induced Dielectric Breakdownmentioning
confidence: 99%