Interlock collapsing ALU for increased instruction-level parallelism

Malik, N.; Eickemeyer, Richard J.; Vassiliadis, S.

doi:10.1145/144965.145794

Cited by 16 publications

(3 citation statements)

References 14 publications

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“…"Fused" ALUs that perform two or more dependent operations at a time increase the amount of computation relative to operand shuffling, such as the common fused multiply-accumulate unit and interlock collapsing ALUs [55,56]. Other proposals cluster instructions together to reduce the communication of operand values to instructions outside the group [57,58].…”

Section: Alus and Bypassingmentioning

confidence: 99%

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Wong

Betz

Rose

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

102

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As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and FPGA substrates. We then use the results of these comparisons to infer how the microarchitecture of soft processors on FPGAs should be different from hard processors on custom CMOS.We find that the ratios of the area required by an FPGA to that of custom CMOS for different building blocks varies significantly more than the speed ratios. As area is often a key design constraint in FPGA circuits, area ratios have the most impact on microarchitecture choices. Complete processor cores have area ratios of 17-27× and delay ratios of 18-26×. Building blocks that have dedicated hardware support on FPGAs such as SRAMs, adders, and multipliers are particularly area-efficient (2-7× area ratio), while multiplexers and CAMs are particularly area-inefficient (> 100× area ratio), leading to cheaper ALUs, larger caches of low associativity, and more expensive bypass networks than on similar hard processors. We also find that a low delay ratio for pipeline latches (12-19×) suggests soft processors should have pipeline depths 20% greater than hard processors of similar complexity.

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Section: Alus and Bypassingmentioning

confidence: 99%

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Wong

Betz

Rose

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

102

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“…In this dissertation, the leading non-speculative data dependency collapsing technique we focus on is instruction fusion. Instruction fusion is a technique used to execute two data dependent instructions within the same time interval through the use of a specialized execution unit which can execute two dependent instructions in a single time interval [30]. Instruction fusion in micro-architecture is well utilized.…”

Section: Non-speculative Collapsing Of Data Dependenciesmentioning

confidence: 99%

Dynamic Dependency Collapsing

Aşılıoğlu¹

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“…Initial experiments with the baseline ll unit design indicated that shadow cache lines were nalized too quickly on general-purpose codes due to RAW dependencies among integer instructions. An important design technique in increasing the performance of general-purpose codes is the use of compound functional units such as the cascaded half-cycle integer ALUs (as done in the triple-issue TI SuperSPARC [2]) and fused 3-operand functional units [9]. (Special handling of dependent integer instructions is also an important part of the MIPS R4000 superpipeline design, where an ALU result can be produced every internal cycle [8].)…”

Section: Extended Fill Unit Designsmentioning

confidence: 99%

A fill-unit approach to multiple instruction issue

Franklin

Smotherman

Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture

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Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility as in superscalars and the absence of complex dependency-checking logic from the decoder as in VLIW. In this design, a stream of scalar instructions is executed by the hardware and is simultaneously compacted into VLIW-type instructions, which are then stored in a structure called a shadow cache. When a shadow cache line contains the instructions requested by the fetch unit, the scalar instruction stream is preempted and all operations in the shadow cache line are simultaneously issued and executed. The mechanism that compacts instructions is called a ll unit, and was rst proposed for dynamically compacting microoperations into large executable units by Melvin, Shebanow, and Patt in 1988. We have extended their approach to directly handle data dependencies, delayed branches, and speculative execution (using branch prediction). This approach is evaluated using the MIPS architecture, and a sixfunctional-unit machine is found to be 52 to 108% faster than a single-issue processor for unrecompiled SPECint92 benchmarks.

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Interlock collapsing ALU for increased instruction-level parallelism

Cited by 16 publications

References 14 publications

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Dynamic Dependency Collapsing

A fill-unit approach to multiple instruction issue

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