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Simulation results are presented for machine implementations using a novel integer ALL7 design that allows parallel execution, in a single cycle, of two interlocked instructions, which because of true data dependency must normally be executed sequentially. This parallel execution is achieved by collapsing the execution interlocks between integer ALU operations as well as between address generation operations, but without increasing the cycle time of the base implementation. Results demonstrate that in integer benchmarks, this new design can provide an overall increase in instruction-level parallelism of more than 7% and up to 19% for the out-of-order and in-order instruction issue, respectively.

This paper presents a simulation-based methodfor verifying coherency in weakly ordered shared memory multiprocessor systems. This methodology requires minimal assumptions regarding the implementation details, such as the coherence protocol and cache line replacement rules. Independence from implementation details for architectural verification is achieved via a technique called data-coloring. The non-determinism arising from weak ordering is resolved by introducing rhe notion of validsets for checking the correctness of memory operations. We contrast our approach with other methods that have been prevalent in the industry and provide implementation details and an example implementation of our methodology.