A simulation-based approach to architectural verification of multiprocessor systems

Saha, Avijit; Malik, N.; O'Krafka, B.; Lin, Jenn-Wei; Raghavan, R.; Shamsi, U.

doi:10.1109/pccc.1995.472515

Cited by 11 publications

(3 citation statements)

References 11 publications

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“…Their complexity advantages for simulation-based verification have been realized in past works [34,35], where such models are also referred to as relaxed scoreboards. Each transition is monitored by a checker, effectively ensuring that the simulated system only performs transitions which are legal according to the model.…”

Section: Memory Consistency Modelsmentioning

confidence: 99%

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McVerSi: A test generation framework for fast memory consistency verification in simulation

Nagarajan

Elver

2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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The memory consistency model (MCM), which formally specifies the behaviour of the memory system, is used by programmers to reason about parallel programs. It is imperative that hardware adheres to the promised MCM. For this reason, hardware designs must be verified against the specified MCM. One common way to do this is via executing tests, where specific threads of instruction sequences are generated and their executions are checked for adherence to the MCM. It would be extremely beneficial to execute such tests under simulation, i.e. when the functional design implementation of the hardware is being prototyped. Most prior verification methodologies, however, target post-silicon environments, which when applied under simulation would be too slow.We propose McVerSi, a test generation framework for fast MCM verification of a full-system design implementation under simulation. Our primary contribution is a Genetic Programming (GP) based approach to MCM test generation, which relies on a novel crossover function that prioritizes memory operations contributing to non-determinism, thereby increasing the probability of uncovering MCM bugs. To guide tests towards exercising as much logic as possible, the simulator's reported coverage is used as the fitness function. Furthermore, we increase test throughput by making the test workload simulation-aware. We evaluate our proposed framework using the Gem5 cycle accurate simulator in full-system mode with Ruby. We discover 2 new bugs due to the faulty interaction of the pipeline and the cache coherence protocol. Crucially, these bugs would not have been discovered through individual verification of the pipeline or the coherence protocol. We study 11 bugs in total. Our GP-based test generation approach finds all bugs consistently, therefore providing much higher guarantees compared to alternative approaches (pseudo-random test generation and litmus tests).

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Section: Memory Consistency Modelsmentioning

confidence: 99%

“…To address the complexity of MCM checking in simulation, relaxed scoreboards (operational models) have been proposed [35,34] to monitor every memory operation's correct behaviour. While this would even allow using real workloads and monitor the system on-the-fly, the test generation method is independent of the proposed checking method.…”

Section: Related Workmentioning

confidence: 99%

McVerSi: A test generation framework for fast memory consistency verification in simulation

Nagarajan

Elver

2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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“…MPTG [19], [20] is another generator that addresses multiprocessor cache coherency verification. The reference machine model of MPTG is a combination of memory hierarchy and its associated coherency protocols and is declarative.…”

Section: ) Test Program Generationmentioning

confidence: 99%

EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

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Generating concurrent test-programs with collisions for multi-processor verification

Adir

Shurek

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.

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A simulation-based approach to architectural verification of multiprocessor systems

Cited by 11 publications

References 11 publications

McVerSi: A test generation framework for fast memory consistency verification in simulation

McVerSi: A test generation framework for fast memory consistency verification in simulation

EDA in IBM: past, present, and future

Generating concurrent test-programs with collisions for multi-processor verification

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