Interlock Collapsing ALU For Increased Instruction-level Parallelism

Malik, N.

doi:10.1109/micro.1992.697011

Cited by 19 publications

(8 citation statements)

References 10 publications

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“…An important design technique in increasing the performance of general-purpose codes is the use of compound functional units such as the cascaded half-cycle integer ALUs (as done in the triple-issue TI SuperSPARC [2]) and fused 3-operand functional units [9]. (Special handling of dependent integer instructions is also an important part of the MIPS R4000 superpipeline design, where an ALU result can be produced every internal cycle [8].)…”

Section: Extended Fill Unit Designsmentioning

confidence: 99%

A fill-unit approach to multiple instruction issue

Franklin

Smotherman

1994

Proceedings of the 27th Annual International Symposium on Microarchitecture - MICRO 27

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Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility as in superscalars and the absence of complex dependency-checking logic from the decoder as in VLIW. In this design, a stream of scalar instructions is executed by the hardware and is simultaneously compacted into VLIW-type instructions, which are then stored in a structure called a shadow cache. When a shadow cache line contains the instructions requested by the fetch unit, the scalar instruction stream is preempted and all operations in the shadow cache line are simultaneously issued and executed. The mechanism that compacts instructions is called a ll unit, and was rst proposed for dynamically compacting microoperations into large executable units by Melvin, Shebanow, and Patt in 1988. We have extended their approach to directly handle data dependencies, delayed branches, and speculative execution (using branch prediction). This approach is evaluated using the MIPS architecture, and a sixfunctional-unit machine is found to be 52 to 108% faster than a single-issue processor for unrecompiled SPECint92 benchmarks.

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Section: Extended Fill Unit Designsmentioning

confidence: 99%

A fill-unit approach to multiple instruction issue

Franklin

Smotherman

1994

Proceedings of the 27th Annual International Symposium on Microarchitecture - MICRO 27

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“…Many DSPs have specialized hardware for common computations in signal and image processing, such as dot product, sum of absolute differences, and compare-select. A number of generalized accelerator designs have also been proposed, such as 3-1 ALUs [22,25], closed-loop ALUs [27], or ALU pipelines [5]. Larger accelerators can support bigger subgraphs and thus enhance the performance advantages.…”

Section: Introductionmentioning

confidence: 99%

Scalable subgraph mapping for acyclic computation accelerators

Clark

Hormati

Mahlke

et al. 2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Computer architects are constantly faced with the need to improve performance and increase the efficiency of computation in their designs. To this end, it is increasingly common to see acyclic computation accelerators appear in embedded processor designs. One major problem with adding accelerators to a design is that it is difficult to generate high-quality code utilizing them. Hand-written assembly code is typical, and if compiler support does exist, it is implemented using only greedy algorithms. In this work, we investigate more thorough techniques for compiling to processors with acyclic accelerators. Where as greedy solutions only explore one possible solution, the techniques presented in this paper explore the entire design space, when possible. Intelligent pruning methods are employed to ensure compilation is both tractable and scalable. Overall, our new compilation algorithms produce code that performs on average 10%, and up to 32% better than standard greedy methods. These algorithms also run in less than one second for more than 98% of basic blocks tested.

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“…A mini-graph processor does not rely on latency reducing ALUs [16,21,22,27], but can exploit them. Support for such ALUs depends on the precise manner in which latency reduction is achieved.…”

Section: Alu Pipelinementioning

confidence: 99%

Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth

Bracy

Prahlad

Roth

37th International Symposium on Microarchitecture (MICRO-37'04)

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A mini-graph is a dataflow graph that has an arbitrary internal size and shape but the interface of a singleton instruction: two register inputs, one register output, a maximum of one memory operation, and a maximum of one (terminal) control transfer. Previous work has exploited dataflow sub-graphs whose execution latency can be reduced via programmable FPGA-style hardware. In this paper we show that mini-graphs can improve performance by amplifying the bandwidths of a superscalar processor's stages and the capacities of many of its structures without custom latency-reduction hardware. Amplification is achieved because the processor deals with a complete mini-graph via a single quasi-instruction, the handle. By constraining mini-graph structure and forcing handles to behave as much like singleton instructions as possible, the number and scope of the modifications over a conventional superscalar microarchitecture is kept to a minimum. This paper describes mini-graphs, a simple algorithm for extracting them from basic block frequency profiles, and a microarchitecture for exploiting them. Cycle-level simulation of several benchmark suites shows that minigraphs can provide average performance gains of 2-12% over an aggressive baseline, with peak gains exceeding 40%. Alternatively, they can compensate for substantial reductions in register file and scheduler size, and in pipeline bandwidth. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

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Interlock Collapsing ALU For Increased Instruction-level Parallelism

Cited by 19 publications

References 10 publications

A fill-unit approach to multiple instruction issue

A fill-unit approach to multiple instruction issue

Scalable subgraph mapping for acyclic computation accelerators

Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth

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