Internally compensated LDO regulator based on the cascoded FVF

Hinojo, José María; Luján-Martínez, C.; Torralba, A.; Ramírez-Angulo, J.

doi:10.1016/j.mejo.2014.02.007

Cited by 11 publications

(5 citation statements)

References 13 publications

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“…The voltage difference between input and output terminals is the minimum voltage required to keep MOSFET in saturation region, which is typically around 50 mV to 200 mV [5]- [8]. Hence, PMOS based voltage regulators are called Low Drop Out (LDO) voltage regulators and their power efficiency is comparable with switching regulators [9]- [11]. The dominant pole can be at input of pass transistor or at the output terminal.…”

Section: Fig 1 Basic Block Diagram Of Linear Voltage Regulatormentioning

confidence: 99%

Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles

Guruprasad

2024

jes

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In his article, a comparative analysis of PMOS and NMOS based linear voltage regulators is presented. An output power of 18 mW is considered in the both cases. In PMOS based regulator, the output voltage is 1.6 V and output current is 11.25 mA, whereas in NMOS, they are 1 V and 18 mA respectively. Firstly, a conventional linear regulator is designed with PMOS as pass element and its stability and various performance parameters are analyzed. SPICE simulation is carried out to measure parameters and they are tabulated for the comparison. Similarly, another linear regulator is designed where pass element is a NMOS transistor. After the analysis of stability and performance parameters, SPICE simulation is conducted. The performance parameters of both regulators are compared and it is found that NMOS regulator exhibits better performance but low dropout feature of PMOS regulator makes it suitable for low power applications.

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Section: Fig 1 Basic Block Diagram Of Linear Voltage Regulatormentioning

confidence: 99%

Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles

Guruprasad

2024

jes

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“…Thus, stability issue is not affected [19] and Q-reduction capacitor is not necessary. Based on (17), the Q factor is relatively constant throughout the full range of load due to the absence of g mp . The Q factor is able to maintain well below 0.92 across the allowable range of I out as illustrated in Fig.…”

Section: Stability Analysismentioning

confidence: 99%

“…However, this results in poor regulating accuracy due to low loop gain, although stability can be achieved without additional compensating capacitor. The modified FVF reported in [17] adopted 4 stacking cascoded transistors to achieve precise regulation (high gain) but it requires a larger voltage headroom which is not suitable for low-voltage applications these days. Therefore, it is very challenging to design an LDO fulfilling all the performance parameters.…”

Section: Introductionmentioning

confidence: 99%

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

Lim

Lai

Tan

et al. 2015

Microelectronics Journal

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“…The objective of many recent LDO regulators has been to improve this FOM. Equation (1) defines the FOM used in [6,7] and the smaller the FOM value, the better the performance.…”

Section: Introductionmentioning

confidence: 99%

“…The objective of many recent LDO regulators has been to improve this FOM. Equation (1) defines the FOM used in [6,7] and the smaller the FOM value, the better the performance. * Correspondence: guruprasad.mit@protonmail.com This work is licensed under a Creative Commons Attribution 4.0 International License.…”

Section: Introductionmentioning

confidence: 99%

A low dropout voltage regulator with a transient voltage spikes reducer and improved figure of merit

Prasad¹,

Shama

2020

Turk J Elec Eng & Comp Sci

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An area efficient output capacitor-free low dropout [LDO] voltage regulator with an improved figure of merit is presented in this paper. The proposed LDO regulator consists of a novel, dynamically biased error amplifier that reduces overshoot and undershoot voltage spikes arising from abrupt load changes. Source bulk modulation is employed to enhance the current driving capability of the pass transistor. An adaptive biasing scheme is also used along with dynamic biasing to improve the current efficiency of the system. The on-chip capacitor required for proper working of the LDO regulator is only 35 pF. The proposed LDO regulator is designed and simulated in 180 nm standard CMOS technology. The LDO regulator exhibits a line regulation of 1.67 mV / V and a load regulation of 100 µV / mA. When load changes from 0 mA to 100 mA in 1 µ s, an undershoot of 148 mV and an overshoot of 172 mV are observed. The measured power supply rejection ratio is 25 dB at 100 kHz. The working of the proposed LDO regulator has been tested under all process corners and Monte-Carlo statistical analysis reveals that it is robust against process variations and local mismatch.

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Internally compensated LDO regulator based on the cascoded FVF

Cited by 11 publications

References 13 publications

Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles

Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

A low dropout voltage regulator with a transient voltage spikes reducer and improved figure of merit

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