Intertrack surface losses in miniature coplanar waveguide on silicon-on-insulator

Abstract

Attenuation has been studied in different-sized coplanar waveguide (CPW) patterned onto silicon-oninsulator (SOI) for three different surfaces between the CPW tracks: silicon dioxide/silicon interface, a hydrogen-terminated silicon surface, and a native oxide. For large-gap CPW (signal track width = 100 µm, gap width = 63.5 µm), selective removal of the silicon dioxide from between the metal tracks reduces losses from 0.79 dB mm -1 to 0.69 dB mm -1 at 50 GHz. The subsequent growth of a native oxide on the silicon surface between the tracks results in losses equal to 0.67 dB mm -1 . For small-gap CPW ( = 2 µm, = 2.5 µm), losses are reduced from 5.6 dB mm -1 to 3.4 dB mm -1 at 50 GHz by selectively removing the silicon oxide between the metal tracks. However, when a native oxide is allowed to grow on the silicon surface between the tracks, the losses increase significantly to 5.8 dB mm -1 . When the native oxide is removed, the losses decrease to those observed following removal of the silicon dioxide. The measurements suggest that the contribution of the intertrack surface losses is the result of free-carrier losses due to a surface inversion layer. The surface-associated losses are proportionally larger as the CPW dimensions shrink-as predicted by modelling. We suggest that technologies employing miniature CPW should take this into account. The native oxide should be routinely removed if possible-implying that 2 appropriate chemically-resistant metallisation be chosen, or fabrication processes should incorporate stable passivation of silicon surfaces between CPW tracks to avoid native oxide growth. Conversely, the increased sensitivity of attenuation to surface effects by shrinking CPW dimensions suggests that CPWbased sensors could benefit from miniaturization.

Passivation of miniature microwave coplanar waveguides using a thin film fluoropolymer electret

“…1 d) and subsequently depositing the fluoropolymer onto both sides of the silicon device layer membrane. Note that in this structure, the BOX was not present due to the nature of the technological process—a condition which we have already observed to cause high losses in suspended miniature CPW 26 . The results indicate that we now have a technological solution to this problem using the thin film fluoropolymer.…”

“…17 b, the energy band bending at the silicon surface causes hole depletion far from the silicon surface—these holes do not contribute to microwave losses in the CPW. In the presence of the charge the depletion width is ~ 6 µm, this is larger than the miniature CPW intertrack spacing where most of the microwave field energy is contained 26 . However, the band bending results in electron accumulation at the silicon interface.…”

“…from 3.5 to 4.6 dB at 50 GHz—the largest change being at higher frequency. The gradual increase in the insertion losses over a period of 1 month can be attributed solely to the increase in surface-associated losses in the miniature portion of the CPW—thought to be due to free carrier accumulation at the intertrack silicon surface 26 . When exposed to air and room temperature over a period of 1 month, the a hydrogen-terminated silicon surface 32 – 34 between the tracks will adsorb water and form what is known as a thin ‘native’ oxide 35 – 37 .…”

“…Since this, studies have been undertaken to understand such losses and their control has been attempted using techniques ranging from surface treatments and thin film deposition to etching intertrack material 13 – 25 . It was recently pointed out that surface-associated losses can be considerable for miniature CPW patterned onto silicon-on-insulator (SOI) wafers 26 . The selective removal of the native oxide from the silicon surface lying between miniature CPW tracks—to leave a hydrogen-terminated silicon surface—can significantly reduce the contribution of surface-associated losses in miniaturized CPW 26 .…”

“…It was recently pointed out that surface-associated losses can be considerable for miniature CPW patterned onto silicon-on-insulator (SOI) wafers 26 . The selective removal of the native oxide from the silicon surface lying between miniature CPW tracks—to leave a hydrogen-terminated silicon surface—can significantly reduce the contribution of surface-associated losses in miniaturized CPW 26 . However, when the native oxide gradually grows back onto the unprotected hydrogen-terminated silicon surface between the metal tracks, the surface-associated losses increase.…”