Inverse lithography technique for advanced CMOS nodes

Villaret, A.; Tritchkov, Alexander; Entradas, Jorge; Yesilada, Emek

doi:10.1117/12.2010111

Cited by 6 publications

(3 citation statements)

References 5 publications

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“…It is large enough to capture the optical effects in the context of the weakspots (several times the optical diameter) but not too large that it degrades runtime. More details on the actual LPE flow including details of stitching and described in [4] Weak Spots …”

Section: Local Printability Enhancement (Lpe)mentioning

confidence: 99%

Model-based SRAF solutions for advanced technology nodes

et al. 2013

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Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.

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Section: Local Printability Enhancement (Lpe)mentioning

confidence: 99%

Model-based SRAF solutions for advanced technology nodes

et al. 2013

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“…Instead, it is viewed rather as a local "repair option" on specific positions in the layout where, e.g., a rulebased assist placement leads to a hotspot. 8) 2.3.2 Assist printability. If we assume that model-based assist placement techniques such as ILT solves the problem of where to place assists, it is still necessary to ensure that the assists will not print.…”

Section: Assist Placementmentioning

confidence: 99%

Optical proximity correction: A cross road of data flows

Bisschop¹

2016

Jpn. J. Appl. Phys.

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This paper reviews the various data flows that occur in the generation and verification of optical proximity correction (OPC) for an optical lithography photomask. First we review the models that are or can be used in the OPC model-calibration flow, with some emphasis on those models that are not yet standard practice. Through an efficient selection of calibration structures, the data amounts needed for model calibrations can be usually kept reasonably small. This is much less the case in the OPC verification step (computationally first and on-wafer afterwards), where data volumes can be very large. Especially the inspection of printed test wafer, where the printability of large number of structures needs to be assessed throughout the intended process window, currently presents important challenges as “hotspot” detection and printability quantification needs to be combined with a short turn-around time. We will discuss some of the approaches that are being employed to deal with these conflicting requirements.

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“…[1][2][3] Inverse lithography technology (ILT), 4,5 as an active approach of RETs, is considered as an effective and economically viable way to meet various challenges in current and future technology nodes. 6,7 To put ILT into practice, various methods have been proposed by academic as well as industrial communities on mask manufacturing rule constraints, 8,9 pattern grouping strategy to accelerate computing, 10 GPU-based hardware accelerated techniques, 11 and mathematical solution methods for the inverse problem. 4,5 In this paper, we focus on improvement of mathematical solution methods, where the computational efficiency is one of the most noteworthy issues.…”

Section: Introductionmentioning

confidence: 99%

Cascadic multigrid algorithm for robust inverse mask synthesis in optical lithography

Lam

Wei

et al. 2014

J. Micro/Nanolith. MEMS MOEMS

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Abstract. Robust inverse mask synthesis is computationally intensive, and its turnaround time continues to rise hand-in-hand with the ever-shrinking integrated circuit feature size. We report the development of a cascadic multigrid (CMG) algorithm for robust inverse mask synthesis, which starts from a relatively coarse mask grid and refines it iteratively in stages, so as to achieve significant speedup without compromising numerical accuracy. Since the CMG algorithm entails frequent changes of the computational grid size, we need to intentionally introduce an analytical circle-sampling technique for modeling the forward lithography imaging and employ an edge distance error as metric to guide mask synthesis. These two techniques work nicely with variable grid sizes and are well suited for our CMG algorithm. As a result, our algorithm achieves more than four times speedup over conventional methods that synthesize a mask on a fixed fine grid. Numerical results are presented to demonstrate the validity and efficiency of the proposed method. © The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

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Inverse lithography technique for advanced CMOS nodes

Cited by 6 publications

References 5 publications

Model-based SRAF solutions for advanced technology nodes

Model-based SRAF solutions for advanced technology nodes

Optical proximity correction: A cross road of data flows

Cascadic multigrid algorithm for robust inverse mask synthesis in optical lithography

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