Investigation of Low Temperature Cu Pillar Eutectic Bonding for 3D Chip Stacking Technology

Tsai, Yi-Chieh; Lee, Chia-Hsuan; Chen, Kuan‐Neng

doi:10.1109/3dic48104.2019.9058877

Cited by 3 publications

(3 citation statements)

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“…Two types of Cu-Sn bonding approaches have been reported: solid-liquid interdiffusion (SLID) bonding and low-temperature solid-state diffusion (SSD) bonding. The bonding temperature of SLID (250°C-280°C) is higher than the melting point of Sn (232 °C), which causes molten Sn overflow and reliability issues [6][7][8]. To solve these issues, the SSD method is employed.…”

Section: Introductionmentioning

confidence: 99%

Low-temperature, short-time, wafer-level bonding for Cu/Sn/Cu solid-state-diffusion interconnect in 3-D integration

Li¹,

Wang²,

Li³

et al. 2023

Phys. Scr.

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In this paper, Cu/Sn/Cu solid-state diffusion (SSD) under low temperature is proposed and investigated for three-dimensional (3-D) integration. Cu and Sn films were deposited by high-efficiency and low-cost physical vapor deposition to fabricate 40-µm-pitch daisy-chain structures. Subsequently, the Cu bump surface was treated with Ar (5% H2) plasma. The Cu/Sn/Cu structure was bonded face to face at 200 ℃ for 15 min. The interfacial composition of the as-bonded dies comprised five layers, Cu/Cu3Sn/Cu6Sn5/Cu3Sn/Cu, with no Sn remaining and no overflow. After annealing at 200 ℃ for 15 min under N2 atmosphere, as the Cu6Sn5 completely transformed into Cu3Sn, the microstructure changed to stable three layers: Cu/Cu3Sn/Cu. Additionally, the average bonding shear strength reached 27.0 MPa, which is higher than that for conventional Cu/Sn SSD bonding. The measured bonding resistance value was maintained at the theoretical value. Moreover, the parabolic growth constant of Cu3Sn reached 1.86×10−15 m2/s. Our study demonstrates the feasibility of using Cu/Sn/Cu SSD for low-temperature, short-time, wafer-level bonding.

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Section: Introductionmentioning

confidence: 99%

Low-temperature, short-time, wafer-level bonding for Cu/Sn/Cu solid-state-diffusion interconnect in 3-D integration

Li¹,

Wang²,

Li³

et al. 2023

Phys. Scr.

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“…Different fine-pitch interconnect bonding methods are contrasted, as shown in Figure 1(c) (Liu et al , 2021a), involving SLID bonding, anisotropic conductive film (ACF) bonding and metal/dielectric hybrid bonding (Lu et al , 2019; Tsai et al , 2019; Tang et al , 2018; Guangming et al , 2017; Kim et al , 2013; Nghiem et al , 2018). SLID faced reliability problems of underfill and solders, with intermetallic compounds appearing in the bonding process, for instance.…”

Section: Introductionmentioning

confidence: 99%

Recent progress on bumpless Cu/SiO₂ hybrid bonding for 3D heterogeneous integration

Kang

Niu

et al. 2022

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Purpose Bumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s continuous development, which achieves the stacks of chips vertically connected via through-silicon via. Surface-activated bonding (SAB) and thermal-compression bonding (TCB) are used, but both have some shortcomings. The SAB method is overdemanding in the bonding environment, and the TCB method requires a high temperature to remove copper oxide from surfaces, which increases the thermal budget and grossly damages the fine-pitch device. Design/methodology/approach In this review, methods to prevent and remove copper oxidation in the whole bonding process for a lower bonding temperature, such as wet treatment, plasma surface activation, nanotwinned copper and the metal passivation layer, are investigated. Findings The cooperative bonding method combining wet treatment and plasma activation shows outstanding technological superiority without the high cost and additional necessity of copper passivation in manufacture. Cu/SiO2 hybrid bonding has great potential to effectively enhance the integration density in future 3D packaging for artificial intelligence, the internet of things and other high-density chips. Originality/value To achieve heterogeneous bonding at a lower temperature, the SAB method, chemical treatment and the plasma-assisted bonding method (based on TCB) are used, and surface-enhanced measurements such as nanotwinned copper and the metal passivation layer are also applied to prevent surface copper oxide.

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“…1. SLID with underfill materials is the most commonly used solution, while intermetallic compounds (IMC) are formed during the SLID bonding process, leading to challenges of reliability, structural stress, and electromigration [4][5][6]. In addition, squeeze out of solders (Sn or In) and the filling capacity of underfill material results in challenges to further shrink the pitch between bonding bumps, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Demonstration of Low-Temperature Fine-Pitch Cu/SiO₂ Hybrid Bonding by Au Passivation

Liu

Chen

Chou

et al. 2021

IEEE J. Electron Devices Soc.

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Investigation of Low Temperature Cu Pillar Eutectic Bonding for 3D Chip Stacking Technology

Cited by 3 publications

References 10 publications

Low-temperature, short-time, wafer-level bonding for Cu/Sn/Cu solid-state-diffusion interconnect in 3-D integration

Low-temperature, short-time, wafer-level bonding for Cu/Sn/Cu solid-state-diffusion interconnect in 3-D integration

Recent progress on bumpless Cu/SiO₂ hybrid bonding for 3D heterogeneous integration

Demonstration of Low-Temperature Fine-Pitch Cu/SiO₂ Hybrid Bonding by Au Passivation

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Investigation of Low Temperature Cu Pillar Eutectic Bonding for 3D Chip Stacking Technology

Cited by 3 publications

References 10 publications

Low-temperature, short-time, wafer-level bonding for Cu/Sn/Cu solid-state-diffusion interconnect in 3-D integration

Low-temperature, short-time, wafer-level bonding for Cu/Sn/Cu solid-state-diffusion interconnect in 3-D integration

Recent progress on bumpless Cu/SiO2 hybrid bonding for 3D heterogeneous integration

Demonstration of Low-Temperature Fine-Pitch Cu/SiO₂ Hybrid Bonding by Au Passivation

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Recent progress on bumpless Cu/SiO₂ hybrid bonding for 3D heterogeneous integration