Investigation of pickup effect for multi-fingered ESD devices in 0.5 µm 5V/18V CDMOS process

Abstract

Pickup effect for 5V NMOS and 18V lateral double-diffused NMOS under electrostatic discharge (ESD) stress is investigated and characterised by a transmission line pulse test system in a standard 0.5 mm 5V/ 18V CDMOS process, respectively. Experimental results show that 5V low-voltage multi-fingered NMOS devices cannot be turned-on uniformly with more added inner pickups and thus the ESD robustness degrades. For 18V high-voltage multi-fingered LDNMOS structures, it is critical to merge all pickups with the P-well guard-ring of the device to achieve uniform current conduction and better ESD performance.Introduction: Electrostatic discharge (ESD) damage to integrated circuits is more severe than ever before as CMOS technology advances. MOS based ESD devices are still one of the best candidates for most ICs owing to easy implementation and dual ESD conduction characteristics. However, there is an intrinsic disadvantage of non-uniform current conduction in multi-fingered MOS devices under ESD stress conditions. Methods like extending the drain or adding an additional mask called salicide block (SAB/RPO) [1] can be used to increase the ballasting resistance and make the current flow more evenly in the unit-finger width. The layout technique of inserting inner pickups in multi-fingered MOS devices to ensure equal base resistance for all the parasitic BJTs was reported more than decade ago [2, 3]. However, Ker found that pickups can directly affect the performance of ESD devices in the other way in some 0.18 mm and 0.13 mm salicide CMOS processes [4,5]. Lee found that a small base resistance of the parasitic BJT in high-voltage multi-fingered LDMOS structures would cause a current crowding effect or current non-uniformity between fingers and thus degrade the overall ESD performance of the device [6]. In this Letter, the ESD performance with a different number of the pickups in multi-fingered 5V NMOS and 18V LDNMOS devices fabricated in 0.5 mm 5V/18V CDMOS processes is studied.

Strengthen Anti-ESD Characteristics in an HV LDMOS With Superjunction Structures

“…This nonuniform turned-on phenomenon means that the anti-ESD robustness of a GGnMOS transistor does not increase linearly with the increase of total device width W tot , which in turn causes a thorny problem in ESD protection circuit design [37], [38]. It is common that in an HV process, the V t 2 value is always far less than the V t 1 value, all of the sub-nMOSTs were turned-on by the first snapback finger, and then the nonuniform turned-on phenomenon is serious.…”

High holding voltage segmentation stacking silicon-controlled-rectifier structure with field implant as body ties blocking layer

“…The parasitic lateral bipolar junction transistors (BJTs) in n-LDMOS structure have different base resistances. Large base resistance leads to earlier turn-on of BJT [18][19][20][21][22][23] and draws large amount ESD current at central position of large area array of finger type layout. The ESD protection ability per unit area was then decreased if we directly extend the layout area of gate-ground NMOS.…”

Influences of source pick-up and well engineering on the ESD robustness of LV process nMOSTs

“…:!! :-:::: t:::': =J In order to effectively solve the non-uniform turned-on problem, a considerable number of literatures [6][7][8][9][10][11][12][13][14] to investigate the substrate pick-up process to solve the problem.…”