Investigation of Ring-TFET for Better Electrostatics Control and Suppressed Ambipolarity

Kumari, Tripty; Singh, Jawar; Tiwari, Pramod Kumar

doi:10.1109/tnano.2020.3038655

Cited by 10 publications

(4 citation statements)

References 27 publications

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“…This occurs because semiconductor carriers obey the Boltzman statics [5]. Numerous studies, including those on the tunneling field-effect transistor (TFET) [6][7][8], impact-ionization MOSFET (i-MOSFET) [9,10], ferroelectric negative-capacitance field-effect transistor (NCFET) [11,12], nano-electro-mechanical field-effect transistor (NEMFET) [13], and feedback field-effect transistor (FBFET) [14][15][16] have offered methods to overcome the SS limitations of MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

Das,

Katta,

Raj

et al. 2024

Phys. Scr.

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The design and performance analysis of a Si-SiGe heterostructure-based double gate feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed HDG FBFET is capable of providing high on current (3×10−4 A/μm) with a large ION /IOFF ratio (3×1011) and is scalable up to 20 nm channel length. Its exceptionally steep switching characteristics (SS〈 1 mV/decade) and ability to switch ON/OFF at lower gate voltage due to the use of smaller band-gap material (Si1−xGex) in channel-2 and drain regions make it suitable for use in low power applications. A significant hysteresis window of 4.99 V is also achieved by the device, which can be extremely helpful for memory applications. Moreover, a comprehensive investigation of the nature of hysteresis in relation to the different device parameters has also been carried out. The designing of the device structure and all of the electrical performance characterization have been done using the Sentaurus TCAD tool.

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Section: Introductionmentioning

confidence: 99%

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

Das,

Katta,

Raj

et al. 2024

Phys. Scr.

Self Cite

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“…As a result, it has not been possible to scale down the power-supply voltage (V DD ) in silicon-based transistors in accordance with the physical scaling of the transistor dimension. Numerous studies [6][7][8][9][10][11][12][13] have proposed remedies to the aforementioned issues. Some of them altered the hitherto typical MOS architectures, while others subtly utilized new device operation principles.…”

Section: Introductionmentioning

confidence: 99%

“…Some of them altered the hitherto typical MOS architectures, while others subtly utilized new device operation principles. Tunnel field-effect transistors (TFET) [6][7][8], ferroelectric negative-capacitance field-effect transistors (NC-FET) [9,10], impact-ionization MOSFETs (i-MOS) [11,12], and nano electro-mechanical field-effect transistors (NEMFET) [13] are some of the devices that have previously been proposed to overcome the Boltzman limitations of MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Design and performance analysis of tri-layered strained Si/Si_1–xGe_x/Si heterostructure DG feedback FET

Das,

Kumari,

Katta

et al. 2024

Phys. Scr.

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This work presents the design and performance analysis of a tri-layered strained Si/Si1−xGex/Si heterostructure double gate feedback field-effect transistor (DG FBFET). The proposed DG FBFET is designed by introducing biaxial strain in the device by sandwiching a Si1−xGex layer between two thin Si layers to provide high ON current as well as ultra-steep switching characteristics. The device offers a significantly high ON current (3.4×10−3 A/μm), high ION/IOFF ratio (∼ 1010), a large memory window of 1.06 V, and an extremely low subthreshold swing (∼ 0.3 µV/decade), which can be very useful for memory and neuromorphic applications. Furthermore, the ON/OFF switching of the device has been accomplished at a lower threshold voltage (0.287V), allowing it to be utilized in low-power electronics. Synopsys TCAD tool has been used to create the device structure and analyze the electrical performances of the device.

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“…ANY researches aim at enhancing the electrical performance of the Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (MOSFET) using new semiconductor materials, manufacturing processes or device structures around the conventional temperature (T) range of, e.g., -25°C to 65-85°C [1]- [7]. Other techniques are based on the simple change of the gate geometry (known as pn junctions engineering among the source/channel/drain regions or simply gate layout changing) of MOSFETs [8].…”

Section: Introductionmentioning

confidence: 99%

The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures

Galembeck

Renaux

Swart

et al. 2021

IEEE J. Electron Devices Soc.

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This paper describes the influence of Longitudinal Corner Effect (LCE effect) and PArallel Connection of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with Different Channel Lengths Effect (PAMDLE effect) of Diamond (hexagonal gate shape) MOSFET in different Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technologies (180nm-Bulk and 1µm-Silicon-On-Insulator, SOI) and in a wide range of high-temperatures (from 300K to 573K). The results have shown (average gains of Diamond MOSFET in relation to standard MOSFET: 60% for saturation drain current, 51% for transconductance, 10% for transconductance-over-drain current ratio etc.) that LCE and PAMDLE effects tend to be similar for CMOS ICs technological nodes used and the different high temperatures. Therefore, we can conclude, for the first time, that LCE and PAMDLE effects are kept active in different CMOS ICs technological nodes and when the Diamond MOSFET is exposed at high temperatures.

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Investigation of Ring-TFET for Better Electrostatics Control and Suppressed Ambipolarity

Cited by 10 publications

References 27 publications

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

Design and performance analysis of tri-layered strained Si/Si_1–xGe_x/Si heterostructure DG feedback FET

The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures

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Investigation of Ring-TFET for Better Electrostatics Control and Suppressed Ambipolarity

Cited by 10 publications

References 27 publications

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

Design and performance analysis of tri-layered strained Si/Si1–x Ge x /Si heterostructure DG feedback FET

The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures

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Design and performance analysis of tri-layered strained Si/Si_1–xGe_x/Si heterostructure DG feedback FET