The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) implemented with diamond layout style (hexagonal gate geometry) are quantified, thanks to the longitudinal corner effect and parallel association of MOSFETs with different channel lengths effect contributions. Futhermore, an accurate analytical drain current model for planar diamond SOI MOSFET for micrometre scale effective channel lengths is proposed and validated. The concept is then extended by 3D simulations for the 150 nm node fully-depleted SOI n-channel MOSFETs.Introduction: Nowadays, silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology is broadly used to manufacture commercial mixed integrated circuits (ICs) for low-power lowvoltage purposes, and numerous new devices have been studied to improve the electrical performance of analogue and digital ICs [1,2].Considering planar CMOS, the diamond layout style (Fig. 1a) is an alternative device for use in analogue IC applications, to significantly enhance the metal-oxide semiconductor field-effect transistors' (MOSFETs') electrical performance, only by layout change, without causing any extra burden to the CMOS manufacturing process used [3,4].
This paper presents an experimental comparative study between the OCTO, Diamond and Conventional Silicon-On-Insulator nMOSFETs (OSM, DSM and CSM, respectively), considering the same bias condition for all devices. The first comparison between the OSM and the CSM counterpart considers the same gate area and the second between the OSM and DSM regards the same geometric factor, in order to verify the benefits of the octagonal gate geometry, that uses the longitudinal corner effect to increase the resultant longitudinal electric field along of the channel, to improve the device performance and consequently to enhance the performance of analog integrated circuits. These characteristics can be observed on the main analog parameters such as drain current in saturation region, maximum transconductance, transconductance by drain current, voltage gain, unity voltage gain frequency and Early voltage.
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