The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) implemented with diamond layout style (hexagonal gate geometry) are quantified, thanks to the longitudinal corner effect and parallel association of MOSFETs with different channel lengths effect contributions. Futhermore, an accurate analytical drain current model for planar diamond SOI MOSFET for micrometre scale effective channel lengths is proposed and validated. The concept is then extended by 3D simulations for the 150 nm node fully-depleted SOI n-channel MOSFETs.Introduction: Nowadays, silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology is broadly used to manufacture commercial mixed integrated circuits (ICs) for low-power lowvoltage purposes, and numerous new devices have been studied to improve the electrical performance of analogue and digital ICs [1,2].Considering planar CMOS, the diamond layout style (Fig. 1a) is an alternative device for use in analogue IC applications, to significantly enhance the metal-oxide semiconductor field-effect transistors' (MOSFETs') electrical performance, only by layout change, without causing any extra burden to the CMOS manufacturing process used [3,4].

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The focus of this work is to validate the drain current analytical model of the Fully Depleted Diamond SOI nMOSFETs, by applying the paired t-test statistical evaluation with experimental data of the six different samples of integrated circuits containing different Diamond SOI MOSFETs and Conventional ones counterparts. Two parameters are considered in this work: maximum transconductance and saturation drain current. We observe that, for the most cases (worst case is around 85% of the repeatability for the saturation drain current), the Diamond drain current analytical model is capable to reproduce a similar statistical behavior than the one observed for the conventional SOI nMOSFET counterpart, considering the same bias conditions and SOI CMOS manufacturing process of the integrated circuits.

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