This doctoral thesis illustrates the studies of the variability and mismatch between "N" type MOSFET devices (nMOSFETs) with hexagonal (DnM), octagonal (OnM) and rectangular (CnM) gate geometry, considering four different types of bias of these nMOSFETs during the ionizing radiation procedure X-ray: I- without electrical bias or with all terminals (source, door, drain and substrate) open (Floating); II- with electrical bias of the devices in the operating state of “on-state” or “closed-switch” (On-state); III- with bias of the devices in the condition of analogue operation or operating as an amplifier (Analog); IV- with device bias in the state-off or “open-switch” operating condition (Off-state). Considering the Floating bias, during the Xray ionizing radiation procedure, it appears that DnMs with an a angle of 90° reduce the mismatch between devices by 40.7% for the threshold voltage (VTH) and 56.8% for the subthreshold slope (SS), respectively, in comparison to the values found in the CnMs counterparts. Considering the On-state bias during the procedure of X-ray ionizing radiation, it is observed that OnMs with an a angle of 90° and a 50% “c” factor improve the matching between devices by 57.4% for VTH and 54.9% for SS compared to those found in CnM counterparts. In the Analog and Off-state bias during the X-ray ionizing radiation procedure, the DnMs and OnMs showed a better matching between devices compared to those obtained with the CnMs counterparts and with a 95% accuracy level. During the procedure of X-ray ionizing radiation in Floating mode, the maximum total ionizing dose (TID) used was in the order of up to 4.5 Mrad. In addition, during ionizing X-ray radiation procedures in On-State, Off-State and Analog modes, the maximum TIDs used were 200 krad for On-State and Analog modes and 20 krad for Off-State mode. Therefore, the Diamond and Octo layout styles can be considered as alternative layout strategies for the implementation of MOSFETs in order to enhance their tolerances to ionizing X-ray radiation, aiming at applications in integrated circuits (ICs) implemented with Complementary Metal-Oxide-Semiconductor (CMOS) manufacturing technology